NAZIL MUHAMMED

32-bit RISC-V Core for Industrial Applications   June 2024

• Architecture design and verilog implementation of a 5-stage RISC-V core with interlocked pipeline stages for the RV32I ISA.

• The processor has support for 37 base instructions and is capable of operating at a frequency of approximately 85 MHz.

• Developed a forwarding unit and pipeline management block to resolve data and control hazards, validated with testbenches covering 8 unique instruction sequences addressing all possible cases of data hazards and 3 instruction sequences for control hazards specific to the conceived architecture.

8-bit pipeline analog to digital converter for IoT applications    April 2024

· This project uses Cadence Virtuoso, a popular software tool for designing electronic circuits,

to create an 8 bit pipeline ADC. The design leverages 180nm CMOS technology, a common method for building integrated circuits.

· The goal of designing a 8-Bit pipeline ADC is to carefully plan its design, connections, and performance to ensure they meet performance standards. The expected results are good and fast while reducing power consumption.

· The main goal is to design efficient 100Msps 8-bit Pipeline ADC.This process has enabled the design of reliable and efficient 8-Bit pipeline ADC that can be used for implementation in IOT applications

Implementation of Dual Port Bidirectional FIFO and generation of Layout   Dec 2024

· This CAD Project documents the design, simulation, synthesis, and layout generation of a Dual-Port Bidirectional FIFO (First-In-First-Out) memory module.

· The project successfully demonstrates the implementation of a dual-port bidirectional FIFO with complete CAD flow from RTL design to layout generation. The design handles asynchronous clock domains properly and includes comprehensive verification.