Neha Bharti
Bangalore
Summary
Senior Design Verification Engineer with around 4 years of experience in GPU IP level Verification for both functionality and performance. Proficient in IP verification methodologies, including UVM and System Verilog.Experienced in development and execution of verification plans, Testbenches, and test cases to validate designs against specifications. Proven track record in initiating and overseeing performance verification plans for diverse GPU projects.Adept at collaborative problem-solving within cross-functional teams, ensuring the delivery of high-quality and efficient solutions.
Overview
7
7
years of professional experience
Work History
Senior Design Verification Engineer
Qualcomm
12.2023 - Current
- Ownership of Performance analysis at subsystem levels of all Premium tier GPUs
- Exposed performance gaps in design & many Testplan bugs early at subsystem levels saving time & efforts which led to left shifting the performance verification
- Ownership of functional verification of multiple new feature on premium tier GPU architectures
- Remodeled a complex TB agent as a module to hit many corner cases scenarios & reproduce post silicon bugs
- Ramping up new team members on Design & verification methodology
Design Verification Engineer
Qualcomm
06.2021 - 12.2023
- Modifying and maintaining the simulation environment for GPU IP Design Verification
- New TB agent addition
- Scoreboard logic updates
- Test development for new feature testing
- Register constraints & scenario updates
- Debugging regression failures for both Directed/ Random tests
- Test hang debugs tracing through the GPU data flow.
- Output mismatches debug with respect to the golden reference model.
- Coordinating with the Design and Behavioral Modeling team to identify and fix bugs in the JIRA task tracker tool.
- Developed the performance verification infrastructure at the subsystem level of the GPU from scratch.
- Perf verification testplan development and conducting review meeting with all stakeholders
- Performance monitor development for subsystem
- Peak performance test case simulation analysis and debugs
Design Verification Intern
Qualcomm
01.2021 - 06.2021
- Assisted in subsystem-level GPU verification, focusing on debugging and regression analysis
- Integration and maintenance of UVC
- Learning and exploring GPU architecture and performance counters.
Telecom Engineer
BSNL
01.2018 - 07.2019
- Responsible for Enterprise business Network Management and troubleshooting for Kolkata zone
- Managed for a critical expansion and upgradation project in UBI-Pan-India
- Worked in to test the feasibility and upgradation of Bandwidth at National level
- Worked in close relationship with the stakeholders to mitigate issues and map the risk to cost analysis
Teaching Assistant
BITS Pilani
- Mentoring and Organizing Lab Orientations
- Coordinating and assisting undergrad students in labs
- Evaluating assignments and lab experiments for Undergrad students
- Conducting and Invigilating Examinations
Education
M.E. - Embedded Systems
BITS Pilani
07-2021
B.Tech - Electronics & Communication
B.C. Roy Engineering College
08-2016
Skills
- IP/Unit level verification
- UVM
- SystemVerilog
- Testbench Development
- Debugging
- Verdi
- VCS
- Industry-Standard VIPs
- Coverage closure
- Performance Analysis
- Analytical skills
- Problem-solving skills
- Communication skills
- Mentorship
- GPU verification
Hobbies and Interests
- Painting
- Badminton
- Traveling
Projects
RISC-V Processor Design and implementation, Verilog, Combination of Structural and behavioral, Single cycle and multi-cycle architecture implementation, Modelsim Design and development of Hand Gesture recognition unit for speech Impaired people, STM32F4 Discovery board, Flex sensor, Bluetooth module, Gyroscope, buzzer, LCD, UART, ADC, I2C, Output shown on Mobile Bluetooth HC-05 app as gesture mapped alphabets, Keil
Languages
- English
- Hindi
- Bengali
Personal Information
Date of Birth: 07/20/94
Timeline
Senior Design Verification Engineer
Qualcomm
12.2023 - Current
Design Verification Engineer
Qualcomm
06.2021 - 12.2023
Design Verification Intern
Qualcomm
01.2021 - 06.2021
Telecom Engineer
BSNL
01.2018 - 07.2019
Teaching Assistant
BITS Pilani
M.E. - Embedded Systems
BITS Pilani
B.Tech - Electronics & Communication
B.C. Roy Engineering College
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