Neha Bharti

• Enabled designers to identify clock domain crossings effectively during RTL development phases.
• Assessed CDC violations and communicated findings to block owner designers for timely corrective actions.
• Conducted extensive hands-on analysis using Spyglass CDC and PLDRC (LINT).
• Updated libraries and input constraints to support CDC flow after RTL alterations.
• Oversaw RTL updates per specifications, ensuring clean results across multiple iterations.
• Secured and archived modifications in development view, establishing baselines within Qualcomm's Uflow process.
• Incorporated verified changes into the integration stream to ensure alignment across projects.
• Performed comprehensive checks pre- and post-delivery to safeguard against disruptions in other users' RTL updates.

• Verified low power design of IP and subsystems to achieve quality results.
• Generated UPF for RTL design, enhancing low power efficiency.
• Enabled VCLP flow, ensuring accurate design implementation relative to power and voltage rails.
• Facilitated VCLP setup across multiple partitions, producing partition-level UPF.
• Conducted manual UPF updates, ensuring alignment with low power design intent.
• Executed lint synthesis and power runs, followed by detailed result analysis.
• Utilized strong debugging skills to resolve VCLP failures efficiently.
• Performed RTL updates and static checks including lint and other release processes.

• Managed clock management unit for multiple IPs, optimizing power and clock gating for enhanced performance.
• Performed synthesis, linting, and CDC analysis for quality assurance.
• Generated setups for static checks, ensuring design integrity and compliance with specifications.
• Checked subsystem-level connections, verifying seamless integration of IP components across the design.

• Designed high-performance chips with low power consumption, delivering bug-free results.
• Executed RTL and baseline deliveries alongside clean CDC and PLDRC results.
• Performed multiple static checks, including PLDRC and CDC, to ensure high-quality outputs.
• Identified static and dynamic critical design issues at RTL and reported findings to design owner.
• Debugged violations in collaboration with core team to resolve issues or obtain waivers by deadlines.
• Generated BIST logic and integrated it from multiple cores for static checks.
• Wrote RTL clock and data constraint files according to design specifications.
• Developed automated scripts for waiver generation and modified design constraints for technology migration.

Executed low power design and RTL integration for 14nm and 7nm technologies, enhancing overall performance and efficiency.

• Applied low power design methodologies with multi-voltage and multi-power domain considerations.
• Integrated hard IPs and subsystems within SoC architecture, contributing to seamless functionality and system cohesion.
• Developed test benches to verify IP design and executed functional simulations.

Revised existing IP designs and developed high-level documents for mixed signal IPs.

• Conducted VCLP runs for UPF, identifying and addressing errors.
• Performed simulation checks for various test cases on silicon oscillators and ADCs.
• Developed comprehensive high-level documentation for finite state machine interfaces and clock/reset implementation, facilitating better understanding and implementation across teams.

• Developed VHDL code for APB bus master and slave functionality, ensuring reliable data transfer.
• Designed APB interface, enabling efficient communication between components.
• Proposed decoder and glue logic design, enhancing SRAM reading capability via APB interface.
• Implemented CRC logic to enhance data integrity in design.
• Replaced analog MTP with digital SRAM from Altera DE0-Nano Cyclone IV FPGA for CAN message transmission.

Role: Responsible for RTL coding and FPGA prototyping

• Created H.264 video codec to enhance video processing capabilities
• Engineered architecture for real-time operation of H.264 codec, improving performance and responsiveness
• Designed CAVLC encoder module in Verilog HDL
• Implemented design on Quartus to configure H.264 with Cyclone-II FPGA, DE2-115 board
• Developed test bench and analyzed simulations of encoder on Xilinx ISE 14.7 tool
• Synthesized RTL codes with Xilinx ISE tools to generate bitstreams.
• Simulated and verified serial communication protocols (UART, I2C, SPI) on FPGA to ensure functional accuracy