NERIC JOEL

Possesses versatile skills in project management, problem-solving, and collaboration. Brings fresh perspective and strong commitment to quality and success. Recognized for adaptability and proactive approach in delivering effective solutions.

• Certification in Data Structures and Algorithms
• Certification from VLSI Workshop
• Certificate in National Cadet Corps (NCC)
• State-Level Runner-Up in Kho Kho

• Design and Development of a Photovoltaic (PV) Emulator (Simulation)

Developed a PV emulator using advanced optimization algorithms (PSO, GA, and QEA) to simulate real-time solar panel behavior undervarying environmental conditions. Improved design efficiency of solar systems with accurate I-V characteristic modeling and dynamic adaptability.

• Building Segmentation Using ResNet-50 and U-Net
  Implemented a deep learning model combining ResNet-50 as a backbone with U-Net architecture for accurate building segmentation in satellite images. Enhanced performance by leveraging transfer learning and advanced image preprocessing techniques.

• Automated Drowsiness Detection with Integrated Lane Positioning System
  Developed a real-time drowsiness detection system using facial landmarks and eye closure analysis, integrated with a lane positioning feature to enhance driver safety. Combined computer vision techniques and sensor data for accurate alert generation and lane deviation warnings.

• Extreme Fast Charging of Electric Vehicles (Simulation)
  Simulated an Extreme Fast Charging (XFC) system using a Dual Active Bridge (DAB) DC-DC converter to optimize power transfer for electric vehicles. Implemented phase-shift control strategies to reduce current stress and ensure voltage isolation for safety and efficiency. Conducted transient behavior analysis to enhance stability and improve converter performance under dynamic charging conditions.

• Ripple Carry Adder Optimization Using MGDI Technique (Simulation)
  Simulated an optimized Ripple Carry Adder (RCA) using the Modified Gate Diffusion Input (MGDI) technique to reduce power consumption, propagation delay, and transistor count. Demonstrated improved power efficiency and compact design compared to traditional CMOS-based RCAs, making it suitable for low-power VLSI applications like mobile and embedded systems.