Summary
Overview
Work History
Education
Skills
Training
Disclaimer
Timeline
Generic

NIKHIL KUMAR K

Hyderabad

Summary

4+ Years of experience in ASIC Verification. Good knowledge on Peripheral protocols such as PCIe, USB. Experience in building verification environment from scratch using Verilog, System Verilog, OVM/UVM methodology. Got Appreciations from Clients on increasing Test coverage, quick response. Experience with simulation, waveform, and other DV tools. Hands-on experience in Test Plan & Test Bench development in UVM environment. Proficient in writing test cases, simulation and debugging. Strong analytical/problem solving skills and ability to guide critical decisions. Passion and hunger to learn new technology every day and drive to getting things done. Good debugging and analytical skills.

Overview

7
7
years of professional experience

Work History

Intel

Wipro
05.2021 - Current
  • Reviewing IP component specification, developing and executing full chip and/or cluster level validation plans.
  • Worked on different subsystems from different chipsets/SOC from Alder, Lunar, Panther Lakes.
  • Providing technical guidance and mentoring junior engineers on the team.
  • Defining and developing testbench, enhancing verification flow and methodologies for validation environment.
  • Have supported in creation of USB Val Diet Environment TAM Domain.
  • Maintained Regression test suite for all PCIE combinations, responsible for all of them to pass.
  • Develop the test cases based on available requirement from different subsystems specifications and verification plans.
  • Gone through the IP level and legacy project test plan to understand verification methodology, features to be covered, and find the Deltas and dependencies at SOC level.
  • Find out the key and new features that needs to be verified. Investigate the scope of work, tests required and dependencies on other teams like Design, Emulation, Power management.
  • Discuss and review the plan SOC leads, Design and IP teams, SOC architects and make sure all the intended scenarios for this feature are covered at SOC.
  • Check other team dependencies on my feature. Plan and schedule the work to meet the project milestones.

Risetime Semiconductor (OPC) Pvt Ltd.
12.2018 - 05.2021
  • Checking regression Test cases failure
  • Debugging regression failures, providing initial analysis, and reporting to leads.
  • Support the verification team by defining & implementing improvement areas for the day-to-day work.
  • Preparing and holding design verification reviews.
  • Got trained on MBIST Protocol from Siemens team.
  • Have used Memory BIST Controller for Validating different memories.
  • Porting of test cases and coverage from legacy projects and modifying as per needs
  • Deliver the sequences and libraries related to my features as required by other SOC teams and supporting with their debug.
  • Work with, and report IP and TB teams to update checkers as per the issues found.
  • And meanwhile come up with necessary workarounds and get the test going.

Education

Secondary School -

The Mother's Integral School
05.2012

B.Tech - Electronics and Communication Engineering

Sreenidhi Institute of Science and Technology
05.2018

DIPLOMA - ECE

Jawaharlal Nehru Govt. Polytechnic
03.2015

Skills

  • HDL Language: Verilog

  • HVL Language: System Verilog

  • HVL Methodology: OVM/UVM

  • EDA Tools: VCS Synopsys, DVE, DVT, Questa Sim

  • Protocol knowledge: PCIe, USB, MBIST, CNVI, Audio

  • Operating System: Linux, Windows

Training

Extensive Training at Jagruthi Technosys, Hyderabad for 6 months.

Disclaimer

I hereby declare that the information furnished above is true to the best of my knowledge. Place: Hyderabad Date: Koppoji Nikhil Kumar

Timeline

Intel

Wipro
05.2021 - Current

Risetime Semiconductor (OPC) Pvt Ltd.
12.2018 - 05.2021

B.Tech - Electronics and Communication Engineering

Sreenidhi Institute of Science and Technology

DIPLOMA - ECE

Jawaharlal Nehru Govt. Polytechnic

Secondary School -

The Mother's Integral School

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