Nilesh Patil
Madhapur,TG
Summary
4 Years of expertise with complicated systems using System Verilog (UVM) as a Design Verification Engineer. Have experience in the design, development, and troubleshooting of analog, digital, and mixed-signal systems. Also write the score and coverage, select the testing tools, create test plans, and establish the testing methodology.
Overview
3
3
years of professional experience
Work History
ASIC Verification Engineer
Helson Software
02.2021 - Current
- Built constrained random UVM test bench from scratch in reusable manner so as to be included in top level verification.
- Strong knowledge of VHDL/Verilog and System Verilog
- Expertise in ASIC verification methodologies such as OVM/UVM
- Experience with debugging and problem-solving on complex designs
- Proficient in scripting languages such as Perl and Python
- Familiarity with test bench automation frameworks and regression setup
- Knowledge of industry-standard tools such as Mentor Graphics, Synopsys, Cadence, and Verilog
- Ability to write test plans, test cases, and test reports
- Familiarity with design for testability and scan architectures
- Strong communication and interpersonal skills
- Worked as Team member Tasks are assigned on individual/Team bases & successfully completed throughout the project.
Verified functionality of unit level LP test case with RTL
Tools: VCS [ Dynamic LP tool], Design Compiler, VC STATIC
Languages: Verilog, VHDL, System Verilog
Power Format: CPF
Internship Trainee
AionSi India Pvt. Ltd.
Bengaluru, KA
05.2022 - 01.2023
- Responsible for involve creating TB architecture, developing different testcases based on functionality and achieving code and functional coverage for various protocols.
- Learned new materials, processes, and programs quickly.
- Completed Projects on,
- Project 1: APB
Roles & Responsibilities:
• Developed class -based verification environment
• Defined Test Plan
• Developed different test cases
• Functional coverage model implementation
Tools & languages used: Questasim, System Verilog
Methodology: UVM - Project 2: AMBA AXI
Roles & Responsibilities:
• Developed class -based verification environment
• Defined Test Plan and Verification Plan
• Developed different test cases
Tools & languages used: Questasim, System Verilog
Methodology: UVM - Project 3: Clock Controller
Roles & Responsibilities:
• Developed class -based verification environment
• Defined Test Plan
• Developed different test cases
Tools & languages used: Questasim, System Verilog
Methodology: UVM
Education
Bachelor of Science - Electronics Engineering
SSVPS College Of Engineering
Dhule, India05.2020
Skills
- HDL: Verilog
- HVL: System Verilog
- Verification Methodologies: Constraint Random Coverage Driven Verification, Assertion Based Verification - SVA TB Methodology:
- UVM Protocols: AXI, APB, AHB, Data Controller, Clock Controller
- DA Tool: Mentor Graphics - Questasim and Xilinx - ISE, EDA Playground
- Programming Languages: C [Datatype Array Pointers Memory Allocation List Queues and stacks Data structure, Functions] C (Good knowledge of OOPs concept, Class, Inheritance, Polymorphism) Operating System: Linux, Windows
Accomplishments
- Developed and verified test cases in Verilog, VHDL, and System Verilog along with UPF/CPF.
- Maintain Regression for Tools.
- Developed Low Power and reset sequence assertions.
- Developed application Level test scenarios.
- Resolved product issue through consumer testing.
Languages
- English
- Hindi
- Marathi
Skills
Programming Languages : C, Perl, C++
Power Format CPF, Language : Verilog, VHDLHVL : System VerilogHVL Methodology : UVMEDA Tools :- Cadence IUS, Synopsys : VCS, Design Compiler, VC LPLinuxs, Window, AMBA
Timeline
Internship Trainee
AionSi India Pvt. Ltd.
05.2022 - 01.2023
ASIC Verification Engineer
Helson Software
02.2021 - Current
Bachelor of Science - Electronics Engineering
SSVPS College Of Engineering
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