Summary
Overview
Work History
Education
Skills
Awards
Valid VISA Details
Certification
Timeline
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Nima K Soman

Nima K Soman

Experienced ASIC Design Verification Professional
Bangalore

Summary

15 years of experience in Front end Digital Design Verification, HW-SW Co-Simulation and Analog verification using HLS models. Been DV Architect, leading development of DV infrastructure for connectivity chips at IP, System and SOC level. Highly self-driven, streamlining deliverables as per organizational goals, inquisitive to learn, collaborate, render quality deliverables are identified to be my greatest strengths.

Overview

17
17
years of professional experience
5
5
years of post-secondary education
1
1
Certification
4
4
Languages

Work History

Principal Design Verification Engineer (Manager Role)

Marvell Technology
04.2024 - Current
  • This role I was assigned with 3 direct reporters. In this Business Unit I am handling
  • Project AquilaA0: Led and innovated the ATB block verification for AquilaA0 at Coherent Tx and full-chip levels—developing assertion automation scripts, resolving tool limitations, and delivering results ahead of schedule through deep analog-digital collaboration and architectural learning.
  • Project Dragonfly: Led the final DV closure for I3C slave block in the Dragonfly SoC under extreme tape-out pressure—resolving critical design gaps, expanding test coverage, and streamlining cross-site validation through emulation and leadership collaboration.
  • Project Aquila: Developed testbench infrastructure to support SW-HW co-simulation of Coherent-lite Line Transmitter analog Phase Detector calibration algorithms on in-phase and quadrature phase skew calibration algorithms.
  • Project Aquila: Led the on-field development of validation CLI scripts, execution, debugging, and deployment activities in collaboration with the Firmware Driver team for customer releases. Conducted knowledge sessions across BU with teams attending from Vietnam, Irvine, Ottawa and Pavia on Line transmitter skew calibration validation plan.
  • Project Aquila: Conducted Coherent-lite line transmitter skew calibration validation, had several business trips to Marvell’s Santa Clara headquarters, California, worked closely with Analog designers from Pavia, Marvell Italy. primary architect for FW team deliverables and customer engagement. Gained technical knowledge using high Bandwidth digital oscilloscope of 50Ghz range from Keysight, used Thermal Silicon to test skew calibration behaviour under process variation.
  • Project: AquilaMacsec – Worked as Coherent-Lite Transmitter 400G subsystem lead for Design Verification, driving high-impact results in the project lifecycle including Gate level simulations, connectivity testing of embedded systems in analogue subsystem using Jasper Connectivity App and DV sign off with code coverage closure.
  • Submitted Paper on DVCON 2025, External skew injection test mechanism to handle Coherent line transmitter skew calibration on electrical layer without optical photodetectors.
  • Initiative on developing ad-hoc group on Formal verification. Mentoring juniors to learn System Verilog assertion basics and exercises on Cadence Jasper Gold tool.
  • Evaluated emerging technologies in design verification space, recommending their adoption when applicable to advance team capabilities.
  • Implemented code reviews and quality checks to maintain high standards of coding practices within the team.
  • Championed the adoption of new verification tools and methods, positioning the team at the forefront of industry advancements.
  • Created reusable testbenches that reduced effort required for future projects, improving overall efficiency.

Principal Design Verification

Marvell Technology
05.2023 - 03.2024
  • Storage and Memory Business Unit – (May 2023 – March ,2024)
  • Developed and implemented IP level testbench to verify Host Management Command Fetcher block from Sub system level testbench using STUBBED RTL for other blocks in NVME system.
  • Developed PCIe driver and checker UVC’s to handle the CMDF block.
  • Developed NVME MFND feature to handle multi-functional namespace ID feature as per NVMe standards but the feature got shelved so couldn’t continue work in this.
  • Worked on verification of PCIe MSI-X interrupt handling using STMF – status manager message handling block within NVME Subsystem.
  • Reproduced silicon bugs on DV environments and confirmed RTL fixes, in collaboration with Design Team.
  • Actively involved in NVMe team recruitment, build and development . The team started with 3 members located in Bangalore and Pune but later this was dissolved due to Business reasons and I received an opportunity with Marvell Connectivity BU due to my past experience in connectivity.

Technical Manager

Mediatek Singapore
06.2022 - 05.2023
  • Worked in Custom Compute Silicon (CCS) SoC development Project. This was a collaborative project between Mediatek and Meta for VR based Product solution. Tasks involved testbench development and SoC level traffic bring up, handing weekly deliverables to customer level interactions.
  • Project CCS: Role involves training and managing team size of 10 at matrix level on usage of developed SOC flow with UVM based testbench, Processor driven C- based testing infrastructure, provide FW flow support and training for subsystem DV engineers in MediaTek across Geography (Vietnam and India team)
  • Project CCS: Development of Firmware flow and infrastructure to setup processor driven verification platform that functions in tandem with system Verilog based environment. Used Python to script the flow and integrate with Mediatek Compile & Simulation flow.
  • Project CCS: Developed Make file flow to incorporate GCC toolchains, call GCC compiler, create objectables and image files for CPU win in Design. Debugging ISA on exception handling testing, instruction ordering and atomicity.
  • Miscellaneous Task: Actively participated into interview panel, hiring and recruiting new DV engineers for the team from Nanyang Technical University, Singapore
  • Miscellaneous Task: Actively engaged in career placement and preplacement conversations with NTU, Singapore.

Staff Engineer

Qualcomm CDMA Technologies
08.2016 - 12.2021
  • Worked as Senior Lead Engineer, to define and specify requirements for verification of feature WLAN-BT Coexistence IP verification, since November 2016.
  • IC ROLE: IP verification: Developed DV infrastructure that includes agents ,monitors,scoreboards,functional coverage models and sequences. Developed test plan and verified first generation BT-WLAN radio coexistence design, integrated within Qualcomm Bluetooth subsystem. Responsible for DV sign off and support Post-Silicon Validation activities. Qualstar for “Timely development and deliverables for Master PTA Grant Protocol verification for Hastings Prime “.
  • IC ROLE: Power Aware simulation of WLAN -BT subsystem using SOC level testbench. Travelled to Chennai Qualcomm R&D centre, learned the Power Management unit block. Developed and executed tests as per the test plan , for block level switch on-off blocks in the system , IPC [inter processor communication] in power domain and operation of peripheral IO interfaces in power on-off mode.
  • Team Lead: IP verification: Developing verification testbench to verify BLE Bluetooth TX Beam forming, BT-WLAN RX Concurrency Dual Link Layer features for BT wearables and IoT applications, in SV- UVM bench. The block was also verified for its 3rd party wifi connectivity capability and LTE connection capability without data traffic. Define and execute verification test plan for IP, Block, Subsystem, and SOC using System Verilog/UVM based testbench and UVCs. Team of 3.
  • Team Lead: IP Development: DV architect [UVM based UVC’s] for Direct memory Access controller - DMA block verification, testbench development, test execution and end to end closure at IP and SoC level for the SoCs WIN chips. This was 2-member team activity. I received an opportunity to lead this. Define and execute verification test plan for IP, Block, Subsystem, and SOC using System Verilog/UVM based testbench and UVCs.
  • Team Lead: Subsystem level verification: Architect and Ownership for vector based DV testbench for DMA access verification at SoC bench with Bluetooth packet processors. The modus operandi involved exercise and ensure the timing accuracy and performance correctness using FW microcode in Verification environment without microprocessor. Team of 2.
  • Team Lead: Co-Simulation: Developed test plan and Verified BT RX diversity at Bluetooth subsystem level testbench with DRM model to leverage down the simulation time. DRM or digital radio model delivered from HLS flows. Handled integration of models and tested system level BT-WLAN coexistence features, involving analog radio antenna model and FEM [Front end model].
  • Validation Support: Rendered validation support by providing inputs on writing CLI’s for DMA validation and bring up.
  • Customer Support Effort: Interacted with Google silicon validation team for post silicon validation of PTA interface algorithm, developed for backward compatibility BT Zigbee 3rd party interface support within Qualcomm Bluetooth modems.
  • Deployed Synopsys ICO – intelligent constraint optimization tool for regression number reduction and improved verification coverage on Coexistence Manager IP block. This activity was done as part of initiative on learning new tools and deployment.
  • Provided Team level technical sessions on WLAN -BT coexistence across Qualcomm MSM and Voice and Music chips business units.
  • Participated in QBUZZ 2018 Maker Challenge with “Tracer 360” that provides direction correction to Blind with pre – installed destination Maps using Artificial Intelligence.
  • Participated in QBUZZ 2019 Paper presentation with the paper titled, ‘SoC performance counter monitor automatic checker’, already in use for BT Coex Manager Block at BT SoC.
  • Presented paper in QBUZZ 2020 on case study of Synopsys ICO engine tool-based simulations for improved and faster coverage closure.
  • Guided and develop junior team members, university interns at several different levels of experience to encourage career growth and talent recruiting. Supported intern onboarding and integration.
  • All the above-mentioned IC Roles and lead roles also involved holding high, medium and low-level DV status presentations as per Qualcomm Project cycle release demands. During this tenure I have worked on more than eleven BT-WLAN Connectivity products.

Senior Verification Engineer

Infinera India Pvt Ltd
05.2012 - 08.2016
  • Post initial Instructor led training from Synopsys on SV and UVM, I have developed testbench infrastructure on PRBS driver and PRBS pattern detecting checkers. These DV blocks where integrated in various projects in the BU for diagnostic stimulus generation and testing.
  • Project IXSH200: Development of standalone Proprietary VIPs in SV based UVM, developing test plan and execution for all the INFINERA Proprietary Network Interconnect IPs fibre optic switches. There are 9 different types of proprietary packet processors between line, client-side traffic and intermediated ROADM. Developed DV infrastructure in UVM based SV benches with agents, monitors, drivers, scoreboards and functional coverage models for the IPs namely XTPM, XTPD, XTFM and XTFD. Learned and closed code coverage using code coverage metrics.
  • Project IXTG101: Reused IP level DV components and environment to sub-system bench. Used the concept of sequence layering to verify the FPGA wrapper for the IXTG101 with end-to-end scoreboard at OTN packet levels. Final Role as Project Lead for 3-member team and responsible for delivering design verification for an IXTG101 FPGA based solution of Infinera Client long haul network equipment’s, supports 100G ethernet packets switching via Serdes, PCIe lanes to OTN lines.
  • Project IXTG101: Developing Validation Plan, writing FW testing programme in python and delivering full end closure for validation of IXTG101. Validated faults, alarms, diagnostic messaging and operational features from Host PCS to CAUI Serdes and CAUI 100g data to Infinera proprietary XTP frames mapping. Once the laser is ON from ONT600 tester then Ethernet II frames are sent through the PCS layer to CFP Transceiver PHY module, where it gets converted to laser. There on testing the Line cards on TIM blocks stacked on the chassis in face deep loopback mode. The FPGA build on eval board is connected in FAC deep loopback and tester statistics at the RX side highlights the health of the Design.

Lead Engineer

Samsung R&D Centre
04.2016 - 06.2016
  • I had a brief innings with this organization with memory verification business unit as design verification team member but I was more interested in contributing to products related to connectivity hence made the career decision to shift from this place.
  • During this tenure I have supervised an intern, curated tasks that involved development of widget-based test and regression execution tool from Linux. Also, Status update on HTML dashboard.
  • I was also doing NVME accelerator verification at interface of flash controller and DDR block. The task was handed over to a junior member while my exit.

Project Engineer

WIPRO Technologies
09.2008 - 07.2010
  • Attended 3 month long intensive training on Verilog and design verification concepts.
  • AMBA AHB Master design verification using external slave memory block in the testbench. Developed BFM and monitors in Verilog and verified this using self-checking testbench.
  • Design emulation on Stratix III board and tested using the NIOS II processor under NIOS IDE embedded platform version8.1. Tests coded in C language. Validated a CAM (content addressable memory) design . Test plan was already available for this this task was to exercise those and understand emulation platform, debug experience using JTAG debugger.

Education

Master of Science - Electrical Engineering

Indian Institute of Technology
Delhi, India
04.2010 - 01.2012

Bachelor of Science - Applied Electronics & Instrumentation

College of Engineering Trivandrum
Trivandrum, Kerala
04.2004 - 01.2008

Skills

  • Optical Transport network standards IEEE 8022
  • Bluetooth Protocol IEEE 80215
  • BLE
  • 15p4 Zigbee device standards
  • AMBA Bus protocols AHB
  • APB
  • AXI
  • PTA External telecom communication protocol
  • I2C
  • I3C
  • SPI - Low Speed IO protocols
  • PCIe High speed protocols
  • NVME Protocol
  • System Verilog
  • UVM
  • Functional coverage
  • Scripting languages proficiency - Python , Perl
  • Gate-level simulations
  • Post-silicon validation
  • Verification planning
  • Coverage-driven verification
  • Hardware-software co-verification/simulation
  • Assertion-based verification
  • Formal verification techniques
  • Power-aware verification
  • Analog mixed-signal verification
  • Constraint random testing
  • Emulation platforms

Awards

Marvell Gold Sponsorship Award: For setting GOLD standards on Aquila Coherent-Lite Line transmitter post -Silicon validation deliverables, mentoring juniors and extracting best outcomes from them with highest quality., Actively engaged in annual performance appraisals, compensation reviews, monthly employee growth discussions with HR and talent recruitment to ensure team satisfaction and growth., Represented Marvell Technology at campus recruitment events, delivering Pre Placement Talks at IGDTU, Delhi., Actively involved in University Curriculum Revamp activity, worked collaboratively with a small team formed by Chairman of Marvell India, Navin Bishnoi., 39 ThankQ awards since March 2020 over various team level and individual contributions., Responsible for DV sign off and support Post-Silicon Validation activities. Qualstar for “Timely development and deliverables for Master PTA Grant Protocol verification for Hastings Prime “., One among 100 women employees selected across Qualcomm development centres for General Management training for a tenure of 6 months, Cohort Batch 2 in the year 2020. Also selected as mentor for Cohort 3 batch in the year 2021., 2014 “U Rock” Award Winner: peer appreciation award given for relentless contribution across projects and good team spirit., Best Performer Q3,2014 For relentless effort as Module DV lead for XTFD block verification., Best Performer Q2, 2015: - IP level DV development and closure of the XTF framer verification and interoperability of the same with various Optical subsystems., Judges’ choice award hackathon October 2015. Innovation on “Android App based Parking lot blocker “.

Valid VISA Details

  • B1/B2 Visa, United States of America

      September 2024 — August 2034

Certification

Professional Certificate Program in Generative AI & Machine Learning from IIT Kanpur year 2024.

Timeline

Principal Design Verification Engineer (Manager Role)

Marvell Technology
04.2024 - Current

Principal Design Verification

Marvell Technology
05.2023 - 03.2024

Technical Manager

Mediatek Singapore
06.2022 - 05.2023

Staff Engineer

Qualcomm CDMA Technologies
08.2016 - 12.2021

Lead Engineer

Samsung R&D Centre
04.2016 - 06.2016

Senior Verification Engineer

Infinera India Pvt Ltd
05.2012 - 08.2016

Master of Science - Electrical Engineering

Indian Institute of Technology
04.2010 - 01.2012

Project Engineer

WIPRO Technologies
09.2008 - 07.2010

Bachelor of Science - Applied Electronics & Instrumentation

College of Engineering Trivandrum
04.2004 - 01.2008

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Nima K SomanExperienced ASIC Design Verification Professional