NITEESH REDDY POLAREDDY

Highly motivated and detail-oriented VLSI postgraduate with strong foundational knowledge in Physical Design (PD) concepts and CMOS digital design. Proficient in ASIC design flow, including floorplanning, placement, clock tree synthesis (CTS), routing, and timing closure. Familiar with industry-standard EDA tools like Cadence virtuoso. Strong understanding of static timing analysis (STA), DFM, low-power design techniques, and design rule checks (DRC/LVS). A quick learner with good analytical and problem-solving skills, eager to contribute to high-performance VLSI design teams and grow in the semiconductor industry.

• Automotive Embedded Software,Pi-Square Technologies
• Digital VLSI Testing, NPTEL
• Introduction to Cybersecurity, Cisco

 Completed PCB Design organized by Reconfigurable Computing Club

 Completed ARDUINO introduction organized by Reconfigurable Computing Club

• ANTICIPATING THE FUTURISTIC LOANS CONFIRMATION USING MACHINE LEARNING
• THERMISTOR TEMPERATURE SENSING ALARM
• DESIGN AND VERIFICATION OF A FINITE STATE MACHINE (FSM) FOR THE I2C PROTOCOL USING 10-BIT ADDRESSING MODE IN VERILOG
• MOBILE JAMMER CIRCUIT, Which attenuates the nearby mobile signals FOOT STEP POWER GENERATION, Generates power using footsteps (Mechanical to Electrical Energy)

• Playing shuttle
• Cricket