Summary
Overview
Work History
Education
Skills
Timeline
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Nitheesh Kumar

Summary

FPGA and RTL Design Engineer with a strong background in RTL design, IP development, and validation. Committed to driving innovation while meeting stringent project timelines and quality benchmarks.

Overview

4
4
years of professional experience

Work History

RTL Design Engineer

Taltech Technologies(AMD Contractor)
10.2024 - Current
  • Developed Vivado IP for Versal AI Edge Series Gen 2 devices.
  • Collaborated with cross-functional teams (architecture, design, verification, marketing) to gather requirements and ensure high-quality IP development.
  • Updated and optimized existing IPs to meet evolving design specifications.
  • Contributed to pre-silicon and post-silicon validation through IP updates, design creation, and bring-up.

Engineer

TechMahindra Cerium Systems(AMD Contractor)
02.2023 - 09.2024
  • Developed Vivado IP for Versal AI Edge Series Gen 2 devices.
  • Collaborated with cross-functional teams (architecture, design, verification, marketing) to gather requirements and ensure high-quality IP development.
  • Updated and optimized existing IPs to meet evolving design specifications.
  • Contributed to pre-silicon and post-silicon validation through IP updates, design creation, and bring-up.

Associate Engineer

TechMahindra Cerium Systems(Intel Contractor)
01.2021 - 01.2023
  • Contributed to the micro-architecture and RTL development of the MUX and DeMUX subsystem.
  • Performed static quality checks, including Lint, CDC, and STA, to ensure design integrity.
  • Debugged waveform issues and resolved critical problems in the MUX and DeMUX subsystem.
  • Developed System Verilog testbench for the verification of AXI IP functionality.
  • Analyzed and compared PPA (Power, Performance, Area) metrics of multiple existing IPs between Intel Agilex and Xilinx devices.

Project Engineer

TechMahindra Cerium Systems
09.2020 - 12.2020
  • Gained expertise in digital design, System Verilog, Lint, CDC, synthesis, STA, and AMBA AXI protocol.
  • Enhanced knowledge of ASIC and FPGA design flows and processes.

Education

Bachelor of Technology - Electronics And Communication Engineering

JNTUA College of Engineering
02-2020

Skills

  • Languages: System Verilog, Verilog, Tcl
  • Protocol: AXI, APB, SPI, UART, I2C
  • Tools: Xilinx Vivado, Xilinx Vitis, Intel Quartus Prime, Spyglass, VCS, Verdi, Modelsim
  • OS and Version control: Linux, Git, Perforce

Timeline

RTL Design Engineer

Taltech Technologies(AMD Contractor)
10.2024 - Current

Engineer

TechMahindra Cerium Systems(AMD Contractor)
02.2023 - 09.2024

Associate Engineer

TechMahindra Cerium Systems(Intel Contractor)
01.2021 - 01.2023

Project Engineer

TechMahindra Cerium Systems
09.2020 - 12.2020

Bachelor of Technology - Electronics And Communication Engineering

JNTUA College of Engineering

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Nitheesh Kumar