Niveditha Puskuri

Project Name : Ikshvaku

Technology : 6nm TSMC, 14 metal layers

Tools : ICC2, Start RC and Primetime.

Macro Count : 40,45

Instance Count : 1.5M& 1.M

Frequency : 2 GHz

Dimensions : Rectangular and rectilinear

Role : Responsible for Block Level P&R Implementation Handled Two blocks from floorplan -to-GDSII (floor planning, Placement, CTS, Routing) and performed all block level sign-off checks Block level in 6nm Technology, TSMC

• Handled PnR flow from Floorplan to Routing and ECOs
• As block is congested, tried different experiments like,partial blockages,keeping congestion effort as high. and hard blockages at notch areas prevent the shorts and DRC’s
• As timing is critical for hold, I have performed clock pulling experiment by keeping less target latency at clock macro pins
• I got a chance to learn about utilization and congestion issues and methods to control them
• Techniques like w.r.t timing we tried with group path and CCD in PNR
• To Met timing, planned multiple techniques like skewing, manual routing to reduce tran, up sizing/down sizing the cells, removing/adding buffer where it is required by checking the margins of timing paths
• Fixed IREM violations by different techniques like cell padding , manually moving the cells,adding buffers on route, splitting the fan out and manual routing techniques.

Project Name : ArdenC0

Technology : 6nm TSMC, 11 metal layers (2RDL layers)

Tools : ICC2, Start RC and Primetime.

Macro Count : Perfro Macro

Instance Count : 1.1M& 1.3M (smu & vdci tiles)

Frequency : 2.24 GHz

Role : Responsible for Block Level P&R ImplementationHandled Two blocks from floorplan -to-GDSII (floor planning, Placement, CTS, Routing) and performed all block level signoff checks

• As block is voltage dominated , so creating of primary and secondary power domains is challenging thing , tried different experiments like multiple power domains by changing the keeping congestion clean
• As timing is critical for hold, I have performed clock pulling experiment by keeping less target latency at clock macro pins
• I got to learn about utilization and congestion issues while creating the voltage domains
• To Meet timing, planned multiple techniques like skewing, manual routing to reduce tran, upsizing/downsizing the cells, removing/adding buffer where it is required by checking the margins of timing paths.
• Fixed IREM violations by different techniques like cell padding, manually moving the cells, adding buffers onroute, splitting the fanout and manual routing techniques
• I have learnt and fixed metal & base DRC violations and LVS violations by following Physical verification guidelines.

Project Name : MI300

Technology : 6nm TSMC, 13 metal layers (2RDL layers)

Tools : ICC2, Start RC and Primetime

Macro Count : 36

Instance Count :212k & 448k (Two smu & one io tiles)

Frequency : 2GHz

• Handled PNR flow from Floorplan to Routing and ECO’s
• I got to learn about utilization and congestion issues and methods to control them
• Did manual Latency and Skew balancing to meet up the timing goals.
• DRV (data trans, data cap, noise, bottle neck, clock SI and double switch) fixes.
• Fixed critical drcs,shorts manually in ECO phase.
• Fixed setup and hold critical paths with different techniques in ECO phase

Client : INTEL

Technology : 10nm sdg74, Intel foundry with 14 Metal layers + RDL layer

Tools : ICC2, Start RC and Primetime

Role : Responsible for Block Level P&R Implementation

Instance Count : 1.5 million (1 Sub system)

Frequency : 1.8GHz Responsibilities:

• Understanding UPF and resolving its related MV violations. Power-mesh was adjusted to meet Static IR drop violations, had to do different floorplan experiments and lot of path groups to meet the timing issues.
• Block was routing critical and removed NDRs for a few clock nets carefully without impacting timing and clock tree quality metrics.
• Adding of new DIC cells to fix the timing at SOC level and building of analog nets.
• Timing fixes for setup by multicycle Paths and in ECO stage fixes done by using clkPULL and clkPUSH

Client : AMD

Technology : 7nm with 14 Metal layers

Tools : ICC2, Start RC and Primetime

Role : Responsible for Block Level P&R Implementation

Macro Count : 24

Instance Count : 925k, 724k (Two Soc tiles)

Frequency : 1.2 GHz

• RTL to GDSII implementation like Floorplan, CTS, Route, LVS & DRC. Challenges faced are because of block dimensions, where it is having lot of notches are creating congestion.
• Followed the N7 floorplan guidelines while placing the macros.
• Reducing the SOCCLK latency was challenging, resolved this issue by applying bounds.
• Routing: We had to address routing-DRCs with Route-guides being created. Timing Violations Are cleaned-up using Prime time in interactive mode.
• Setup and Hold violations in critical paths are analyzed and closed very carefully.
• Calibre BaseDRC’S & BaseLVS was cleaned at Floorplan stage, it’s the first check point for the N7 floorplan guidelines implemented while placing the macros