NK Sindhu

Enthusiastic Electronics and communication Engineer, focused in the field of VLSI with excellent oral and written communication skill. Organized and motivated employee eager to apply time management and organizational skills. To secure a responsible career opportunity to fully utilize my training and skills, while making a significant contribution to the success of the company.

• Design and simulation packages: Cadence Virtuoso, synopsys VCS, PSpice, Xilinx
• Programming Languages: Verilog, System Verilog, System Verilog Assertions, C programming
• Digital and Analog : Digital electronics, CMOS, FPGA, STA, Microcontroller, microprocessor and RISC-V.
• Protocols - AHB,APB and I2C.
• Methodologies :UVM

• Scouts and Guide
• Athlete
• Worked in E-cell
• Toastmasters -Treasurer

• Toastmasters - ISC winner at club for two consecutive years.
• Performer of the month at maven silicon for the month October-2023

• Start Of the month by Maven Silicon
• Certification of Arduino UNO Programming- Oct 2019
• TEDxVVCE- Oct 2019

Advanced VLSI Design & Verification Trainee- June 2023 - Present

Maven Silicon

• RTL Coding using Synthesizable constructs of Verilog, FSM based design, Simulation, CMOS Fundamentals Code Coverage, Functional Coverage, Synthesis Static Timing Analysis, Assertion Based Verification using System Verilog Assertions.
• Utilized UVM methodology for building verification environment components like drivers, monitors.

Design Engineer Intern Sep 2021-July 2022

Vivarthan Technologies

Utilized UVM methodology for building verification environment components like drivers, monitors.

• Worked on Xilinx to run simulation for basic gates.
• Created layouts for AND and OR gate.

1. Verification of Dual Port RAM using SystemVerilog Verification Environment.

Description :  Created a Verification Plan for Dual Port RAM to verify it and perform functional coverage (Used Synopsys VCS)

Responsibilities:

Created a Verification Plan for the following features: Reset, Read, Write and Read+Write Strategized by defining Test cases and Coverage Models.

Created a Verification Environment using SystemVerilog.

Generated Coverage Report using Functional Coverage Model.

2.Design & Verification of Modulo 10 Up-Down Loadable Counter using SystemVerilog Verification Environment

 Description :  Wrote the design for Modulo 13 Up-Down Loadable Counter  and Created a Verification Plan for the same to verify it and perform functional coverage (Used Synopsys VCS)

Responsibilities:

Developed RTL code for the design Created a Verification Plan for the following features: Reset, Clock, Mode, Load.

Strategized by defining Test cases and Coverage Models Created a Verification Environment using SystemVerilog.

Generated Coverage Report using Functional Coverage Model.

3.Router 1x3 – RTL design and Verification

 Description :  The router accepts data packets on a single 8-bit port and routes them to one of the three output channels, channel0, channel1 and channel2. 

HDL: Verilog HVL: SystemVerilog TB Methodology: UVM EDA Tools: Questasim and ISE

Responsibilities:

Architected the block level structure for the design Implemented RTL using Verilog HDL. Architected the class based verification environment using SystemVerilog Verified the RTL model using SystemVerilog. 

Generated functional and code coverage for the RTL verification sign-off. Synthesized the design.

1. ASIC implementation of RISC-V core.

RISC V using PULP platform to minimize the power and increase the efficiency.