Omang Mahure
Bengaluru
Summary
Adept Principal Application Engineer with a proven track record at Cadence Design Systems and Microsemi, showcasing expertise in Clocking technology and project leadership. Excelled in high-stakes environments, achieving successful tape-outs and pioneering Intel's first Automotive project. Demonstrates exceptional skill in PPA optimization and Power Optimization , underpinned by a strong foundation in floorplanning techniques and Clocking Methodology across different Technology nodes(N7, N3, 1222, 1276, 1278) and DCLS.
Overview
8
8
years of professional experience
Work History
Principal Application Engineer
Cadence Design Systems
Bengaluru
02.2019 - Current
- Catered multiple projects in Intel (Thunder Bay, Oyster Bay, LNL, CameroDrive, CGC-A0, CGC-B0).
- AMD :- Early TR at AMD with 2 Block conversions
- ThunderBay and Oyesterbay :- Was resposible for 7 blocks each (NoC - Network on Chip Tiles) (N7)
- Implemented Flex-H, Multi-Tap CTS for all the partition to help PPA
- LNL Media :- Plorification and TR activity (N3)
- CameroDrive :- Single handled lead Project with 4 Core cpu blocks with Automotive flow (DCLS using Midas), First Automotive activity in Intel (Test chip taped out). (1222.3)
- CGC-A0, CGC-B0 :- High Frequency Cores (5,4Ghz) Block conversion and succesfull tape-outs (1278)
- Grounded hold closure, CTS recipes, clocking methodology for all the partitions.
- Grounded Ideal Hold Fixing for required partitions
- AMD - 2 block conversion on short roadmaps (N3).
Physical Design Engineer
Microsemi (Now Microchip)
Bengaluru
08.2017 - 02.2019
- Handled 3 Blocks
- Netlist to GDS Implementation
- Responsible for Floorplanning,PNR, and PV
Education
Bachelor of Science - Electronics And Communications Engineering
BK Birla Institute of Engineering And Technology
Pilani07-2017
Training - Physical Design
CDAC Mohali
Mohali09-2016
Skills
- Clocking technology
- Clocking methodology
- Hold closure
- PPA
- Floorplanning techniques
- Power Optimization
- PnR
- DCLS
Accomplishments
- Author (Paper), Selected in DAC -2025
- Have Published several Cos Solution and Articles
Timeline
Principal Application Engineer
Cadence Design Systems
02.2019 - Current
Physical Design Engineer
Microsemi (Now Microchip)
08.2017 - 02.2019
Bachelor of Science - Electronics And Communications Engineering
BK Birla Institute of Engineering And Technology
Training - Physical Design
CDAC Mohali
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