Padmasri Sirikonda

Creative and tech savvy VLSI Professional with over 8+ years of progressive experience in Design Verification recognized for high productivity and efficient task completion. Excels in specialized skills including UVM (Universal Verification Methodology), System Verilog and functional coverage analysis. broad range of Design Verification domain by crafting and executing meticulous verification plans, simulations, and tests. Proven ability to combine vision, ingenuity and strong technical acumen with well-versed project experience and leadership qualities to support deliverables, Implementation and integration of several validation techniques.

• Honored with Best student Award in School.
• Received 'Honorable Mention' for the project 'Google: A World of Bliss' in NASA AMES Space Settlement Contest 2012.
• Received 'Honorable Mention' for the project 'Titan: A Nestle in the Future' in NASA AMES Space Settlement Contest 2013.
• Received student excellence award at 32nd International Space Development Conference held at San Diego, California.

Verification of PI5 Sub-System, INTEL, 11 months, The subsystem has a four-ported 16 Lane PCIe Gen5 IP., 

Roles & Responsibilities:

Integration of RAL model & Verification RAL model for different endpoints.

Developing test scenarios for RAL frontdoor & backdoor boundary access.

Developing & validating various scenarios., Developing sequences & checkers.

Developing new constrained random testcases., Functional coverage coding & analysis. 

Verification of DDR PHY Testchip, INTEL, 8 months, DDR PHY Testchip is to test the LPDDR4/5 analog content of the PHY., Defining & executing verification plan from specifications., Integration of RAL model & Verification RAL model., Integration of BFM., Developing testbench components., Automating Regression scripts & regression environment., Code coverage and functional coverage analysis. Verification of MODULAR PHY IP, INTEL, 14 months, The Modular PHY architecture is designed to support several PHY standards., Debugged test failures., Validated the DFx features of the IP in isolation mode., Responsible for providing test pattern to Soc Team., Improved Fault Coverage using the Synopsys tool ZOIX., Automation Scripts for RAL updates. Verification of HTX_PAI IP in HDMI Transmitter Sub-System, NXP, 7 months, HTX_PAI is HDMI Transmitter Parallel Audio Interface., Defining & executing verification plan from specifications., Developing testbench components., Automating Regression scripts & regression environment., Code coverage and functional coverage analysis. Verification of Chroma Sub-Sampler IP in Display Controller Sub-System, NXP, 8 months, Chroma Sub-sampling is a technique of compression., Defining & executing verification plan from specs., Developing new constrained random testcases., Debugging & enhancing existing testcases., Enhancing verification testbench components., Automating Regression scripts & regression environment. Verification of Context Load IP in Display Controller Sub-System, NXP, 4 months, It is a Display controller sub-system which is used to send a compressed Video., Debugging simulation failures, identifying bugs, proposing fixes., Automating Regression scripts & regression environment., Coverage Analysis. Verification of SoC based on ARM Cortex M4 series, Renesas, 4 months, The Design MCU integrates multiple series of software and pin-compatible ARM-based 32-bit MCUs., Listing down the features and development of verification plan., Testcase Debugging and enhancing existing testcases., Automating Regression scripts & regression environment., Coverage Analysis.

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• Performance evaluation of multi-branch multi-hop networks with Kth best relay selection, International conference on Communication and Signal Processing (ICCSP), 04/06/16, Chennai
• Outage Analysis of AF based multi-hop multi-branch networks with Kth best relay selection, International conference on Wireless Communications, Signal Processing and Networking (WiSPNET), 03/23/16, Chennai
• Google: A World of Bliss, 31st International Space Development Conference (ISDC), 05/24/12, Washington, D.C
• Titan: A Nestle in Future, 32nd International Space Development Conference (ISDC), 05/23/13, San Diego, CA

DRDL (Defense Research and Development Laboratory), Hyderabad, Telangana, 2 months, IC Fabrication Techniques, Shri Lakesh Bhaleraw (Scientist 'D')