Palash Jain

Design Experience

• Built a strong foundation in analog layout through hands-on work across 22nm to 3nm nodes at Intel and Capgemini.
• Delivered signoff-ready layouts for RF and analog IPs including LDO, VREF, and HBM/DDR.
• Gained experience working on high-speed, power-sensitive blocks and closing physical verification.

Exposure to EDA Tools

• Daily user of Cadence Virtuoso layout suite with understanding of tool behavior in regression and validation contexts.
• Actively supporting validation for Animate and BAP integration with APR flows, ensuring regression stability and overall flow usability.
• Comfortable scripting in SKILL and Shell to support validation and minor flow enhancements.

Automation

• Developed automation to streamline regression setup and improve validation turnaround.
• Enhanced the Next-Gen VDRC validator to support customer-specific constraints.
• Created scripts for performance testing, EXL to MXL migration, and AutoVia flow validation.

Problem Solving & Customer Focus

• Regularly engaged in debugging QoR issues and creating custom workarounds under tight deadlines.
• Provided automation support and data analysis during new feature validation, improving team efficiency.