Summary
Overview
Work History
Education
Skills
Timeline
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Pallab Pran Dutta

https://www.linkedin.com/in/pallab-pran-dutta-71336188/

Summary

SoC DFT design engineer with 4.5 years of hands-on experience in DFT architecture, MBIST insertion and validation, RTL integration and ATPG . Proven ability to implement robust test strategies that ensure high fault coverage and efficient post-silicon validation. Adept at cross-functional collaboration, troubleshooting silicon failures, and delivering first-pass success in high-performance designs.

Overview

5
5
years of professional experience

Work History

SoC DFT Design Engineer

Intel
Bangalore
07.2024 - Current
  • Developed and collaborated the definition of microarchitecture features of several partition, subsystem, and stacks under DFT being designed (including TAP, SCAN, MBIST) , achieving 99% test coverage
  • Executed RTL integration of complete DFT features for multiple partitions and stacks for server SoCs in coordination with design , physical design and verification teams
  • MBIST insertion and BAP level validation for multiple memory blocks across 3 SoC products
  • Planned and implemented memory repair architecture for multiple repairable memories blocks across 3 SoC products
  • Collaborated and supported manufacturing and post-silicon team in delivering test patterns and providing support on silicon bring up and debugs.
  • Worked with cross-functional teams to clean up SCAN DRC , SGLINT , Clock domain crossing and caliber violations
  • Supported and owned setting up DFT flows for multiple Intel in house and industry standard tools for DFT integration across 2 SoC products
  • Worked on SD feedback by implementing ECOs on RTL freezed designs
  • Resolved UPF issues for DFT partitions for each RTL release as per SD feedback

Intern

Intel
Bangalore
01.2020 - 07.2024
  • Scan chain extraction, DRC analysis ,coverage analysis and TestCoverage improvement
  • ATPG pattern generation, simulation, and fault analysis for Stuck-at, At-Speed (transition & small-delay-defect), IDDQ, and cell aware tests.
  • Gate Level Simulations on ATPG patterns

Education

B.Tech , Electronics & Communication Engineering -

National Institute of Technology , Silchar

M.E , Microelcetronics -

Birla Institute of Technology , Pilani

Skills

  • Spyglass DFT
  • Verilog
  • Verdi
  • Tessent TestKompress
  • Tessent MemoryBIST
  • Quick Synth

Timeline

SoC DFT Design Engineer

Intel
07.2024 - Current

Intern

Intel
01.2020 - 07.2024

B.Tech , Electronics & Communication Engineering -

National Institute of Technology , Silchar

M.E , Microelcetronics -

Birla Institute of Technology , Pilani

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Pallab Pran Dutta