PANCHAKARLA NEELIMA

Working as a Full-Custom Analog and Mixed Signal Layout Designer for more than 5.10 years and having hands-on experience in 3nm, 5nm, 7nm, 28nm,65nm,130nm, 180nm, and 90nm (SOI) technologies for various foundries like TSMC, GF, UMC and Intel.

Project- Negative Voltage Regulator-GF 130nm (SOI) - BGR, Chargepump, Oscillator, Level shifter, Comparator.

Project- Hermes-GF 130nm (SOI) -LNA, PA, Harvester Switch, SPDT, LP resonant CMOS, Reference Generator, Butterworth filter, Comparator, HP regulator, LP rectifier, HP rectifier, Filters, 100Khz oscillator.

Project- Fully Integrated Voltage Regulator-TSMC 3nm -Reference generator, Bias generator, Resistor ladder, Clock generator.

Project- Low Jitter PLL -TSMC 3nm- AFS, Charge pump, Speed adjustment block.

Project- Continues Time Linear Equalizer- P1278(RibbonFet)- Attenuator, Rterm, Bias circuit, ntl switch, ntl comparator, Common Shifter.

Project- Integer PLL-TSMC 28nm PFD, VCO, Divider, Buffer.

Project-Design and Development of NAVIC receiver- UMC 65nm- Single-ended LNA, Single to Differential Ended LNA, Mixer, Buffer.

Project-10 Bit Single Ended SAR ADC for Biomedical Applications-TSMC 180nm-Comparator, Switches, Bias generator, Standard cells for logic gates, D-FF, Transmission gates.

Project-DC-DC Converter for Micro Scale Thermal Energy Harvesting-TSMC 180nm- Buffers, Resistor banks, Capacitor banks, Comparators, Relaxation Oscillators, Voltage dividers, Voltage Sampling, Flip-Flops, Shift registers.

• Cadence Virtuoso
• Custom compiler
• Genesis (L, XL, GXL)
• Caliber
• Assura
• PVS