Summary
Overview
Work History
Education
Skills
Websites
Current Position
Timeline
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Pankaj Saini

Pankaj Saini

Bengaluru

Summary

Dynamic professional seeking challenging assignments in Signal Integrity, Board Design, Compliance Testing, Product Development, Electrical Validation, and Project Execution within reputable organizations in Manufacturing and Electronics sectors.

Overview

13
13
years of professional experience

Work History

Senior Member of Technical Staff

AMD
Bengaluru
10.2024 - Current
  • Full ownership of UFS electrical characterization from test plan creation to report sign-off.
  • Develop and execute test plans covering MIPI M-PHY, UniPro, and UFS standards.
  • Build and automate test environments using Keysight instruments, ValiFrame, and Python/SCPI scripting.
  • Create and adapt test scripts from UniPro protocol flows, ATE/DFT sequences, and compliance patterns.
  • Perform end-to-end PHY validation (TX jitter, RX JTOL, CTLE/DFE tuning, IL/RL/TDR, eye diagram analysis).
  • Drive post-silicon debug and provide actionable feedback to Design, SI, DV, and Analog teams.
  • Act as single point of accountability coordinating across internal and external stakeholders.

Senior Staff Engineer

Marvell India
Bengaluru
01.2023 - 10.2024
  • As a Post-Silicon Validation Engineer, I work closely with cross-functional teams, including design, verification, and software teams, to bring up Ethernet switch ASICs that support up to 25/50/100Gbps SerDes.
  • My role involves validating the design, developing and executing test plans, and troubleshooting issues to ensure that the ASIC meets the required functionality and performance standards.
  • In addition, I am responsible for writing automation scripts using Python to automate testing and improve efficiency.
  • Working in a fast-paced environment, I strive to deliver high-quality results within tight timelines, while ensuring effective communication and collaboration with my team and stakeholders.

Senior ASIC Engineer (Post Silicon Validation)

NVIDIA
Bengaluru
03.2020 - 12.2022
  • As a Post Silicon Validation Engineer, I collaborated with cross-functional teams (Design, Verification, and Software) to validate high-speed interfaces.
  • Additionally, I developed Python automation scripts to streamline testing processes.

Product development engineer- Signal & Power Integrity

UST Global
Penang
11.2016 - 02.2020
  • Hspice simulation for various topology such as USB 3.2 (Gen 1 & 2), OPIO, PCIe, Sata, CNVi, I3C, DDR3/4 etc.
  • Time/Frequency domain analysis for High speed interfaces
  • Working with E.M. field solvers (quasi-static and full wave), time and frequency domain simulation tools like SIWAVE, HFSS, HSPICE
  • Layout review for high speed interfaces
  • Good in Printed Circuit Board (PCB) layout or electrical package design techniques
  • Good fundamental knowledge in Signal Integrity
  • Familiar with, and fundamental understanding of lab measurement equipment like Oscilloscopes, TDR, Vector Network Analyzer (VNA), etc
  • Familiar with statistical analysis (DOE)/JMP tool

Hardware Design Engineer

The Tata Power Company Limited - Strategic Engineering Division (Tata Power SED)
Bengaluru
12.2012 - 11.2016
  • Designing of Hardware module from requirement specifications
  • Estimating system power budget, Design of voltage regulators
  • Preparing detailed design document
  • Schematic entry in Cadence OrCAD
  • Defining board layout constraints, routing guidelines
  • Defining board stack up, impedance rules
  • Performing signal integrity analysis
  • Reviewing the PCB layout
  • Preparing engineering BOM
  • Preparing detailed board bring up and validation plan
  • Assisting in performing system level compliance tests and safety tests

Education

Bachelor of Technology - BTech - Electrical, Electronic and Communications Engineering Technology/Technician

Kurukshetra University
Kurushetra
04.2012

Skills

  • Test plan development and execution, post-silicon debug and root cause analysis, system integration and protocol–PHY correlation, collaboration with SI, DV, analog, and ATE teams, standards compliance (MIPI, JEDEC UFS)

Websites

Current Position

SMTS- Post silicon validation at AMD

Timeline

Senior Member of Technical Staff

AMD
10.2024 - Current

Senior Staff Engineer

Marvell India
01.2023 - 10.2024

Senior ASIC Engineer (Post Silicon Validation)

NVIDIA
03.2020 - 12.2022

Product development engineer- Signal & Power Integrity

UST Global
11.2016 - 02.2020

Hardware Design Engineer

The Tata Power Company Limited - Strategic Engineering Division (Tata Power SED)
12.2012 - 11.2016

Bachelor of Technology - BTech - Electrical, Electronic and Communications Engineering Technology/Technician

Kurukshetra University

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Pankaj Saini