PARIKSHIT DHODAPKAR
Associate Director / Engineering Manager
Pune
Summary
Encouraging manager with over 15 years of experience in the semiconductor industry with talents for team building, leading and motivating, as well as excellent customer relations aptitude and relationship-building skills. Proficient in using independent decision-making skills and sound judgment to positively impact company success. Dedicated to applying training, monitoring and morale-building abilities to enhance employee engagement and boost performance.
Technical experience based on Front End RTL design and SoC integration across a wide range of domains Automotive, mobile, IoT, consumer electronics, bitcoin.
Overview
15
15
years of professional experience
4
4
years of post-secondary education
1
1
Language
Work History
Associate Director / Engineering Manager
Sondrel Ltd
Remote (Pune) & Hyderabad
04.2021 - Current
- Brought about paradigm shift in organization's project execution workflow by single handedly adopting practice of Requirements management using JamaConnect
- This involved convincing and training Sondrel engineers as well as customer
- Managed and mentored Design team (along with bigger Verification team due to unavailability of Verification Manager for 1 year) and successfully guided them to high performance
- Collaborated with engineering and design teams to implement defined SoC features
- Evaluated and selected vendors for engineering projects
- Implemented best practices for recruiting focusing on making hiring process a cherish able experience for candidates while achieving goal of highlighting the organization’s uniqueness.
- Assisted senior leadership in managing all aspects of team responsibilities and operations.
Technical Manager / Project Manager
Tech Mahindra Cerium Systems
Remote (Pune)
08.2020 - 04.2021
- Guided, coached and lead project team, delegating tasks and evaluating performance and progression of project pace. Technical leadership mostly based on Spyglass quality checks
- Helped various teams for recruiting as lead interviewer
- Guided, coached and lead project teams, delegating tasks and evaluating performance and progression of project pace.
- Liaised between business and technology units to manage delivery schedules for applications.
Project Lead
LnT Technology Services Ltd
Pune
04.2018 - 08.2020
- Planned, executed, and controlled assigned projects, ensuring work performed complied with contractual requirements.
- Owned integration of IO pads and pin-muxing including scripting for same. This invariably amounted to ownership of entire top-level stitching. This scripting also incorporated scan mux in pin muxing
- Owned Lint and major stakeholder in Spyglass CDC analysis
- Driving QA
- Worked with DFT team to integrate DFT blocks – helped them with connectivity with other modules and top-level integration
Technical Lead
Cyient Ltd
Pune
05.2017 - 03.2018
- Hands-on Individual Contribution for customer projects and flow improvements
- Interviewing candidates
Senior Engineer
Open-Silicon Research Pvt. Ltd
Pune
01.2014 - 05.2017
- Individual contributor and mentor
- Development of synthesizable memory models for carbon prototyping (virtual prototyping)
- Front-end RTL designer for projects - ASIC for IoT, SoC for wearable domain
Project Engineer & Senior Engineer
Wipro Ltd
Pune
06.2010 - 01.2014
- Individual contributor in projects for RTL design, Spyglass quality checks, FPGA prototyping
- Testing of Samples of two taped out devices of SoC series - Tested evaluation samples of two derivatives on Advantest Tester at Yokohama, Japan
- Also created evaluation report along with other necessary documentation
Trainee Engineer & Project Engineer
Dexcel Electronics Designs (P) Ltd
Bangalore
10.2008 - 06.2010
- Involved in FPGA based design
Field Applications Engineer
FE Global Electronics Pte. Ltd
Pune
05.2008 - 09.2009
Education
PG Diploma - VLSI Design
08.2007 - 02.2008
Bachelor of Engineering - Electronics & Telecommunications
08.2003 - 06.2007
Skills
Strategic Engineering leadership
Accomplishments
- Synthesizable Memory Models for Virtual Prototyping” – individually authored and presented at Microprocessor Test and Verification Conference (MTVCON), Austin, USA, December 2014. Now part of IEEE Xplore Digital Library: https://ieeexplore.ieee.org/document/7087243?arnumber=7087243
- Successfully completed “Initiating and Planning Projects”, an online course authorized by University of California, Irvine offered through Coursera
Timeline
Associate Director / Engineering Manager - Sondrel Ltd
04.2021 - Current
Technical Manager / Project Manager - Tech Mahindra Cerium Systems
08.2020 - 04.2021
Project Lead - LnT Technology Services Ltd
04.2018 - 08.2020
Technical Lead - Cyient Ltd
05.2017 - 03.2018
Senior Engineer - Open-Silicon Research Pvt. Ltd
01.2014 - 05.2017
Project Engineer & Senior Engineer - Wipro Ltd
06.2010 - 01.2014
Trainee Engineer & Project Engineer - Dexcel Electronics Designs (P) Ltd
10.2008 - 06.2010
Field Applications Engineer - FE Global Electronics Pte. Ltd
05.2008 - 09.2009
C-DAC, Pune - PG Diploma, VLSI Design
08.2007 - 02.2008
University of Pune - Bachelor of Engineering, Electronics & Telecommunications
08.2003 - 06.2007
Technical Experience
RTL Design (ASIC and FPGA) and debugging | QA checks – Lint and CDC (Spyglass) | DFT – Functional Interface | Manual ECO implementation in netlist | FPGA Validation | Gate Level Simulation – debugging | System Design using soft processor | Verilog | VHDL | Board Level Debugging
Project Tools Expertise
· JIRA | Jama Connect | TaskTop | Basic knowledge of MS Projects
· Worked on most version managements tools – GIT, CVS, SVN, ClearCase
Technical Experience
RTL Design (ASIC and FPGA) and debugging | QA checks – Lint and CDC (Spyglass) | DFT – Functional Interface | Manual ECO implementation in netlist | FPGA Validation | Gate Level Simulation – debugging | System Design using soft processor | Verilog | VHDL | Board Level Debugging
Project Tools Expertise
· JIRA | Jama Connect | TaskTop | Basic knowledge of MS Projects
· Worked on most version managements tools – GIT, CVS, SVN, ClearCase
Technical Experience
RTL Design (ASIC and FPGA) and debugging | QA checks – Lint and CDC (Spyglass) | DFT – Functional Interface | Manual ECO implementation in netlist | FPGA Validation | Gate Level Simulation – debugging | System Design using soft processor | Verilog | VHDL | Board Level Debugging
Project Tools Expertise
· JIRA | Jama Connect | TaskTop | Basic knowledge of MS Projects
· Worked on most version managements tools – GIT, CVS, SVN, ClearCase
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