Summary
Overview
Work History
Education
Skills
Certification
Languages
Interests
Timeline
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Parth Joshi

Parth Joshi

Bengaluru

Summary

  • Engineer in Semi-conductor Industry striving towards knowledge and excellence.
  • Have 6.5+ years experience as a Design Verification Engineer.
  • Specialized in UVM and System Verilog for developing design verification environment.
  • Experienced in Code/Functional Coverage and Formal verification.
  • Experienced in Gate Level Simulations (GLS).

Overview

7
7
years of professional experience
1
1
Certification

Work History

Senior Engineer

Qualcomm
Bengaluru
09.2021 - Current
  • Working with WLAN PHYTOP DV team for WiFi Physical layer design verification for 802.11 a/n/ac/ax/be/bn protocols.
  • Leading the verification for PHY layer Debug features like ADC Capture/Event Capture/DAC Playback/ATB for PhyTop Subsystem
  • Leading the DV efforts for block level verification of FFT/IFFT blocks
  • Working on Gate Level Simulations (GLS) for multiple projects, developing the entire setup from scratch, verifying DC/PD netlists and SDF timing verification for BTO signoff.
  • Part of Systems Hardware team under WRD - Working on JUNO and REMY Prototype Platforms to test and implement at FPGA level the features of new Wi-Fi generations.
  • Leading and driving Block level testplan development and execution. Creating new Testbench elements from scratch for each new block or feature and drive the whole DV effort for that block.

IP Verification Engineer

Intel
Bengaluru
12.2017 - 09.2021
  • Was part of IP verification team for the Intel’s Server Chipset group.
  • Worked on Error Handler IP serving as a PCIe function in Server SoCs in multiple configurations (RCiEP, RCEC).
  • Worked with Architects to understand features to be implemented and verified at IP level.
  • Assessed and drove IP level testplan development and execution. Worked with the design team to correct defects and test issues.
  • Created new Testbench elements such as constraints, sequences, scoreboard/checkers as per the feature ask/requirement.
  • Drove the Code and Functional coverage testplans for IP testplan signoff.

Education

M.Tech - Digital Communications

Vellore Institute of Technology
Vellore
01-2016

B.E - Electronics And Communications

Gujarat Technical University
Ahmedabad
01-2014

Skills

  • Verilog, SystemVerilog, UVM, Perl, Python
  • PCIe 40, AMBA (AXI, AHB), Wifi 11a/n/ac/ax/be/bn
  • GIT, Perforce, Clearcase

Certification

  • Advanced VLSI Design and Verification - Maven Silicon Institute, Bangalore - Apr'17 to Nov'17

Languages

  • English, Hindi, Gujarati

Interests

  • Football, Badminton, Movies and TV Shows, Bike Rides

Timeline

Senior Engineer

Qualcomm
09.2021 - Current

IP Verification Engineer

Intel
12.2017 - 09.2021

M.Tech - Digital Communications

Vellore Institute of Technology

B.E - Electronics And Communications

Gujarat Technical University

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Parth Joshi