Pavan Vishnu Naidu B

Training and Skills:

• Trained in digital electronics concepts with hands-on experience in Verilog.
• Currently working in DFT (Design for Test) stream for Intel account.
  

Project-1 (Intel, OCT’22 – JUL’23):

• Assisted in ATPG tasks, generating test patterns using Tessent tool commands in Linux environment.
• Developed models for compiling blackbox modules, elaborating designs, and simulating stuck-at and transition fault patterns.
• Contributed to MBIST insertion and pattern generation by reading Verilog files using Tessent.
• Acquired debugging skills using DVE and Verdi tools.
• Gained experience with shell scripting for automation and design validation.
  

Project-2 (Intel, AUG’23 – DEC’23):

• Conducted ATPG tasks, generating test patterns and performing coverage analysis using Tessent.
• Gained proficiency in simulating patterns for various test sets to ensure design integrity.
  

Project-3 (Intel, JAN’24 – APR’24):

• Collaborated with validation team to understand DFX validation process.
• Assisted in debugging diverse test cases using Verdi, enhancing validation efficiency.
• Developed proficiency in shell scripting for automation of validation processes.
  

Project-4 (Intel, MAY’24 – Current):

• Managing gate-level simulations and debugging using Verdi and DVE.
• Supporting ATPG-related tasks and conducting thorough coverage analysis.
• Gained expertise in using various Tessent Shell commands for efficient DFT operations.
  

• Gained hands-on experience in various front end development tools, software, and techniques to contribute effectively to multiple projects.
• Developed an e-commerce website using HTML, CSS, JS, and frameworks such as React-js.
• Created a YouTube-like UI utilizing styling tools like Bootstrap.