Payal Rodi
Bengaluru
Summary
Determined, hard-working and self-motivated individual, with strong focus in architecture and micro-architecture understanding. Worked on ARM CPU and Intel GPU IPs, along with hands-on experience in RTL debugs. Background of M.Tech in VLSI , worked in ARM and currently in Intel, with overall 7+ years of experience.
Overview
8
8
years of professional experience
Work History
Graphics Design Verification Engineer
Intel Technology Pvt. Ltd.
05.2022 - Current
- Responsible for performance verification of compute pipeline at Cluster and GT level for integrated,
discrete and AI/ML graphics
- Cluster majorly focussed on compute thread dispatch pipeline and LSC(load-store cache) units
- Leading team of 3 members , responsible for task planning for multiple projects, understanding micros
and discussing with architects and designers to have missing gap filled
- Understanding of new features and it's impact on performance
- Discussing new content with content development team and asking for required micros ,to meet
verification deadlines
- Taking ownership ,to drive LSC(load store cache) micros across various clusters , and having mixed
traffic scenarios with complicated target calculation understanding
- Contributed on complex feature verification like mid thread preemption across projects
- Driving workgroup, to understand gap ,between real workload and directed micros, along with workload
team , which helped ,to fill lot of gaps prior project execution
- Debugging and root-causing RTL issues , trying to corelate, how competitor performs in certain areas
and discuss on improvements with designers
- Understanding performance metric measurement tool and using it ,to reduce ,debug turn-around time
- Exploring newer areas of performance verification like chicken bit to find bugs
- Implementing occupancy coverage for fifo, to have deeper level of visibility, in structures, which affects
performance directly
- Driving bug escape analysis for previous and on-going projects, across various clusters and GT to fix
the gaps
- Contributed on LSC related SoC performance debugs
- Helping performance modelling team to corelate RTL performance figures with model , if any mis-
corelation, then help them debug
- Responsible to drive performance initiative meetings , motivating engineers to contribute new ideas ,to
improve efficiency and work on them
- Mentoring interns and ramping up on project execution on compute side
- Handling intern hiring process(shortlisting resumes and interview ) , was part of ORG level campus
hiring process , also contributed in interviewing candidates for team
Senior CPU Verification EEngineer
ARM embedded Pvt. Ltd.
10.2021 - 04.2022
- More focussed verification for bug hunting, led to find CAT-A bug , which was even discovered to be an
issue in older CPUs
- Developed generic occupancy coverage framework for internal RTL structures like arbiters, buffers, fifo,
queues etc., to understand how much of them are occupied with existing stimulus. Did analysis and
identified few areas to be stressed more. Framework is been widely used across projects and different
IPs(CPU and interconnects)
- Stress verification around buggy areas, from past projects and new features, led to find multiple bugs
on cpus
- Mentoring junior engineers
CPU Verification Engineer
ARM embedded Pvt. Ltd.
10.2018 - 09.2021
- Worked on ARM Cortex A profile cores, targetted to mobile and server markets
- Task planning and execution for cpu verification, by understanding micro-architecture and architecture
specifications, discussing with designers and software team ,to align requirements ,within project
timeframe
- Contributed new stimulus in micro-architecture areas like, load_store unit and data prefetchers
- Contributed new stimulus in architecture areas like, RAS and virtualization
- Identifying stimulus holes, through bug escapes analysis and fixing quickly within project timelines
Identifying coverage holes and tweak stimulus accordingly
- Contribution on improving RIS tools , in terms of providing timely feedback to improve tool efficiency
- Worked on CHI protocol checker, to make it synthesizable on emulation platform, along with different emulation stakeholders, this was also recognized as, piece of work ,useful for other verification teams in ARM , also selected for poster presentation in Global engineering conference 2021 in ARM. This activity aided verification inorder to find protocol violation issues at system level
- Experience in mentoring interns and new joinees , conducted various ramp-up sessions for new joinees and knowledge sharing seesions on CPU debugs across teams
Graduate Verification Engineer
ARM embedded Pvt. Ltd.
07.2017 - 09.2018
- Worked on ARM's first multi-threaded CPU and contributed on RAS feature verification
- Focussed stress verification around CPU and cross feature validation which helped to discover new
bugs ,in stable areas
- Understanding and tweaking Random instructor generator (RIS) tool to find bugs in weekly regressions
- Hands-on experience, on RTL debugs, through tarmac flow and waveforms
- Contributed in ideas to improve on automation of infrastructure based on verification needs
Graduate Technical Intern
Intel Technology Pvt. Ltd.
07.2016 - 05.2017
- Worked on, post-silicon performance verification ,in PDG Client architecture team ,work involved, post
silicon performance tuning and architectural experiments, based on next generation Intel client platforms.
- Analyzed last level of cache, on-chip coherent interconnect, integrated on-chip memory, DRAM and
Graphics core for performance impact
- Working on critical architectural and design experiments, having direct impact , on upcoming next
generation platforms, focusing on utilization of performance counters to have visibility towards architectural behaviors
Education
M.Tech - VLSI
Vellore Institute of Technology
Vellore06-2017
B.E - Electronics
SAKEC, Mumbai University
Mumbai, India06-2014
Skills
- Technical: Computer architecture, Graphics (compute/GPGPU) architecture, ARM architecture, Functional verification, Performance verification, RTL debugging , worked on CPU/GPU at cluster-level/IP-level, Basics of AMBA (ACE/CHI) protocols
- Soft-skills: Effective communicator, problem solver, goal-oriented team player ,with strong aptitude for learning and long-term thinking , good leadership and time management qualities
Publications
Poster presentation selected for Global Engineering Conference 2021 ,in ARM on, "Synthesizable CHI-protocol checker"
Skills
Computer architecture, Graphics (compute/GPGPU) architecture, ARM architecture, Functional verification, Performance verification, RTL debugging , worked on CPU/GPU at cluster-level/IP-level, Basics of AMBA (ACE/CHI) protocols, Effective communicator, problem solver, goal-oriented team player ,with strong aptitude for learning and long-term thinking , good leadership and time management qualities
Languages
English
Bilingual or Proficient (C2)
Hindi
Bilingual or Proficient (C2)
Marathi
Bilingual or Proficient (C2)
Timeline
Graphics Design Verification Engineer
Intel Technology Pvt. Ltd.
05.2022 - Current
Senior CPU Verification EEngineer
ARM embedded Pvt. Ltd.
10.2021 - 04.2022
CPU Verification Engineer
ARM embedded Pvt. Ltd.
10.2018 - 09.2021
Graduate Verification Engineer
ARM embedded Pvt. Ltd.
07.2017 - 09.2018
Graduate Technical Intern
Intel Technology Pvt. Ltd.
07.2016 - 05.2017
M.Tech - VLSI
Vellore Institute of Technology
B.E - Electronics
SAKEC, Mumbai University
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