PIRANGI GIREESH

• Process Governance & Auditing: Serve as a Lead Internal Auditor for all embedded engineering projects, ensuring 100% alignment with ISO 9001 and CMMI Level 5 standards.
• Audit Excellence: Successfully executed over 150 peer and release audits, verifying project deliverables, code quality, and documentation accuracy prior to client delivery.
• PMP & Risk Management: Conducted comprehensive PMP audits and risk audits to evaluate project health, identifying potential bottlenecks, and ensuring mitigation plans were active and effective.
• Root Cause Analysis (RCA): Facilitated cross-functional teams in performing Root Cause Analysis (RCA) for nonconformities, implementing corrective and preventive actions (CAPA) to drive continuous process improvement.
• Customer Satisfaction (CSAT): Led CSAT validation processes, analyzing client feedback and performance metrics to ensure project outcomes met or exceeded stakeholder expectations.
• Embedded Domain Expertise: Tailored QA processes specifically for embedded systems lifecycles, ensuring compliance in high-stakes environments like Aerospace and Industrial Control.

Testing and validation across seven hardware revisions (Rev A to Rev G), ensuring consistent accuracy for voltage, mV, T/C, and RTD inputs. Conducted accuracy testing and bug verification at each stage to move the module from the initial prototype to a production-ready Golden Revision.

Sharing the reports in LTTS standard format with the client.

Prepared a comprehensive Bill of Materials (BOM) for the Honeywell HC900 UAI module redesign project, documenting all components required for PCB assembly. For each component, the BOM captured the part number, manufacturer name, component description, electrical specifications (voltage rating, current rating, tolerance), package type (SMD/through-hole), quantity per board, and approved vendor list. Additionally, I verified the RoHS (Restriction of Hazardous Substances) and REACH compliance status of every component to meet international environmental regulations. Performed life status checks to identify any end-of-life (EOL) components, and flagged them for replacement through the Value Engineering process. The BOM served as the master reference document for procurement, manufacturing, and component engineering activities throughout the project. Conducted net-level verification on the UAI module PCB layout to confirm that every electrical connection defined in the schematic was correctly implemented in the physical board design. Verified continuity of all critical nets, including I2C bus lines (SDA, SCL) connecting the STM32 MCU to the EEPROM, SPI bus lines (MOSI, MISO, SCK, CS) connecting the MCU to the Watchdog IC, and analog input signal paths for voltage, millivolt, thermocouple, and RTD channels. Checked for unintended short circuits between adjacent nets, and open circuits caused by missing or broken traces. Power distribution nets (VCC, GND) were verified across the entire board to ensure that all components receive the correct supply voltages. This netlist verification was performed prior to PCB assembly to ensure zero wiring errors on manufactured boards. After the hardware is ready, I conducted a systematic visual inspection of fully assembled UAI module PCBs prior to power-on testing, using magnification tools to examine solder joint quality and component placement accuracy. The inspection covered the entire board surface, checking for solder bridges between adjacent pads or pins, cold solder joints with insufficient wetting, missing components, incorrect component orientation or polarity reversals for diodes and electrolytic capacitors, tombstoning of small SMD components, and physical damage, such as cracked components or PCB delamination. Any defects identified during visual inspection were documented and sent for rework before electrical testing, preventing potential board damage from powering up a defective assembly.

• Developing STM32 MCU-based firmware for the Honeywell ControlEdge HC900 Universal Analog Input (UAI) module (900U02 SIL UIO) — a full redesign of a 25–30-year legacy PLC product used in industrial process control applications.
• Driving architectural redesign necessitated by FPGA component obsolescence; the new design targets a 5x latency reduction from 500 ms to 100 ms and achieves IEC 61508 SIL-2 functional safety certification, with built-in advanced diagnostics and a SIL-certified microcontroller. •
• Implemented EEPROM interfacing via I2C protocol to store factory calibration data in non-volatile memory, enabling reliable calibration retention across power cycles, aligned with HC900 module design standards for redundant factory
• Write — sends calibration data from the MCU to the EEPROM and stores it permanently.
• Read — retrieves stored calibration values from EEPROM every time the module powers on.
• Erase — Clears specific memory locations before writing new calibration data.
• Integrated Watchdog IC via SPI protocol to enforce hardware-level fault detection and safe-state recovery, a critical requirement for SIL-2 safety compliance, and per-channel safety shutdown functionality.
• Collaborated on the full product lifecycle redesign: legacy hardware analysis, new firmware architecture, peripheral integration (I2C, SPI), and validation within a safety-critical industrial automation environment.
• I have prepared the SSD document for the UAI project and finalized the Software Design Document (SDD) following the successful validation of seven hardware revisions (Rev A–G), ensuring all firmware optimizations for noise reduction and accuracy were accurately documented for production.