Pooja Rawat

Project Title: Neural Network Accelerators
Type: In-House Project

Project Overview:
Designed and developed an AI accelerator incorporating a RISC-V processor core integrated with a custom-designed Matrix Vector Threshold Unit (MVTU) to enhance the execution efficiency of neural network operations. The design specifically targets Binary Neural Networks (BNNs), offering significant performance gains and power efficiency for edge-AI applications.

Key Features:

• Acceleration of computationally intensive operations such as matrix multiplication, convolution layers, fully connected layers, pooling, batch normalization, and sign function layers — all optimized for binarized neural networks.
• Seamless integration of the MVTU to support parallelism and high-throughput processing of binary data streams.

Responsibilities:

• Authored detailed documentation for various functional design blocks, ensuring clarity for development and verification teams.
• Designed and implemented the RTL for the MVTU block using Verilog/SystemVerilog.
• Integrated the MVTU with the top-level RISC-V processor-based accelerator module.
• Developed a comprehensive testbench environment and test cases to verify IP functionality, edge conditions, and integration correctness using industry-standard verification tools and methodologies.

Project Title: Microcontroller (MCU) Development
Client: Fermonic Design

Project Overview:
Engineered a microcontroller-based embedded system tailored for real-time processing and control in resource-constrained environments. The MCU was designed to provide a balance between low-power consumption and high performance, making it highly suitable for applications in the Internet of Things (IoT) and embedded control domains.

Responsibilities:

• Formulated an exhaustive verification test plan for IP-level modules within the MCU architecture.
• Designed and implemented directed and constrained-random test cases to ensure thorough functional coverage and verification completeness.
• Performed gate-level simulations (GLS) to validate post-synthesis netlists, ensuring timing correctness and identification of functional mismatches introduced during synthesis and optimization phases.
• Analyzed simulation results and debugged design issues in close collaboration with the RTL and synthesis teams.

Project Title: BOW (Bunch of Wires)
Client: Analog Port

Project Overview:
The Bunch of Wires (BoW) interface is a standardized die-to-die parallel communication protocol designed for high-bandwidth, low-latency data transfer between dies within the same package. It offers an optimal balance between throughput, design complexity, and packaging cost, making it ideal for chiplet-based architectures. BoW enables scalable and modular SoC designs by allowing heterogeneous die integration with simplified interface requirements.

Responsibilities:

• Designed and implemented Finite State Machines (FSMs) for multiple functional blocks within the BoW interface to manage data flow control, synchronization, and protocol compliance.
• Created a detailed verification test plan outlining functional coverage goals and corner-case scenarios for unit-level blocks.
• Developed and executed extensive test cases to validate each unit’s functionality under various operational.
• Collaborated closely with the architecture and integration teams to resolve design and verification issues.

Project Title: RISC-V Core Development
Type: In-House Project

Project Overview:
Designed and implemented a custom RISC-V processor core targeting embedded system applications and domain-specific compute tasks. The core was optimized for flexibility and extensibility, enabling support for custom instruction sets while maintaining a focus on low-power operation and area efficiency.

Responsibilities:

• Developed a comprehensive block-level verification test plan covering all key functional units within the RISC-V core (e.g., ALU, register file, pipeline stages, memory interface).
• Implemented directed and random test cases to validate the correctness, performance, and corner-case behavior of individual modules.
• Worked with the RTL design team to review architecture specifications and ensure accurate mapping of design functionality to verification scenarios.
• Participated in debugging sessions to analyze simulation failures, identify root causes, and propose RTL fixes.