POOJASHREE S

As a dynamic, team-spirited, and performance-driven engineering professional, I’m seeking a challenging position to leverage my skillsets in production management, Planning, OTD to Customers. And bring my technical acumen and passion for continuous improvement to a forwardthinking organization

• Have successfully completed workshop on EMBEDDED SIGNAL PROCESSING using ARMCORE IN KRIYA by PSG College Of Technology, 2021.
• Have successfully completed workshop on Intel FPGAs for Embedded, AI/ML and Heterogeneous Computing Applications by Intel, 2023.
• Have successfully completed workshop on AI Based ROBOTICS in PRAVEGA conducted by IISC Bangalore, 2022.
• Participated in KIKI CENTRE OF TECHNOLOGY, IFB GET MANUFACTURING EXCELLENCE PROGRAM, 2024.

• Password Based Door Locking System
  Keil IDE, Embedded C, 8051 Microcontroller
  Duration: Aug 2022 – Oct 2022
  – Designed and implemented a secure digital door lock using a keypad and password verification.
  – Programmed using Embedded C and interfaced hardware via Keil IDE.
• Hospital Management System
  MySQL
  Duration: Oct 2022 – Nov 2022
  – Developed a relational database to manage patient data, appointments, and billing.
  – Ensured proper normalization and efficient SQL queries.
• Voice-Based Examination for Visually Challenged Students
  Python, Raspbian OS (Raspberry Pi)
  Duration: Jan 2023 – Mar 2023
  – Built an audio-enabled exam system allowing students to hear questions and respond by voice.
  – Utilized speech recognition and synthesis for full interaction.
• Driver Drowsiness Detection System
  Python, OpenCV
  Duration: Feb 2023 – Mar 2023
  – Created a real-time facial monitoring system to detect driver fatigue using eye and head tracking.
  – Used OpenCV with Haar Cascade classifiers for detection.
• Design and Implementation of High-Speed Carry Look-Ahead Adder for Image Processing Applications
  Verilog, Intel Quartus Prime
  Duration: Sep 2023 – Mar 2024
  – Designed a fast CLA adder to enhance performance in image processing applications.
  – Simulated and validated timing using Verilog in Quartus Prime.

I, Poojashree S, do hereby confirm that the information given above is true to the best of my knowledge.

Place: Coimbatore
Date: 10 June 2025