Summary
Overview
Work History
Education
Skills
Publications
Quote
Timeline
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Poonam Gawatre

Poonam Gawatre

Hyderabad

Summary

Experienced Engineer with a demonstrated history of leading VLSI Standard Cells IP,DRAM Memories Verification for DDR4, DDR5, LPDDR4, LPDDR5
Organized and dependable lead successful at managing multiple priorities with a positive attitude. Willingness to take on added responsibilities to meet team goals.

Overview

5
5
years of professional experience

Work History

Senior Engineer , DEG Design

Micron Technology
09.2019 - Current
  • Leading Standard Cells Design and Library Characterization engineering team to successfully complete DDR4,DDR5,LPDDR4 LPDDR5, HBM Memory projects on time.
  • Promoted teamwork and demonstrated effective communication skills to improve collaboration among personnel.
  • Monitored employee performance to keep projects on task.
  • Mentored and coached entry-level and junior engineers to improve talent and boost skill levels.
  • Trained and mentored junior engineers, providing guidance and direction.

Stdcells Characterization Engineer

Soctronics Technologies
01.2018 - 09.2019
  • Performing characterization for various channel lengths across different voltage thresholds [VT] like Low Voltage Threshold[LVT], Super Low Voltage Threshold [SLVT], Regular Voltage Threshold [RVT],High Voltage Threshold [HVT].
  • Merged Extracted RC Netlist generation from Back End GDS and CDL Database.
  • Performing Characterization for various PVT corners.
  • Generation of Timing and Power Views.
  • Timing Views: Non Linear Delay Modelling [NLDM], Composite Current Source Modelling CCS Delay /CCS Power/CCS Noise
  • On chip variation: Liberty Variation Format [LVF], Advanced On Chip Variation [AOCV].
  • Power Views: Power Grid Views [PGV] using Voltus IC Tools consisting of EMIR Information.
  • Ansys Apache Library Views CDEV, PWCDEV and SPCURRENT.
  • Consolidation of Release Packet with all views provided by Backend and Front End team.
  • Quality Analysis of release packet for reliability and accuracy purpose.
  • Maintaining through documentation of product database and work performed.
  • Post Release customer support.

Education

Engineer Trainee - Custom Layout Design

VEDA IIT
Hyderabad,Telangana, India
01.2018

Master in Technology - VLSI Design

Ramdeobaba College of Engineering And Management,
Nagpur, Maharashtra, India
07.2017

Bachelor in Engineering - Electronics And Telecommunication

Shri Sant Gajanan Maharaj College of Engineering A
Shegaon, Maharashtra,India
05.2014

Skills

Programming Languages: C, C,Verilog, VHDL

Scripting Languages: TCL, Perl, Shell

EDA tools : Calibre, StarRC, Apache Power Library, Voltus, Spectre, Cadence Virtuoso, Liberate ,Liberate_LV, Solido Variation Designer,

Solido Characterization Suite ,Solido Crosscheck,Primetime,Finesim SPICE simulator

Data Reporting Tools: Confluence, Splunk enterprise dashboard

Technical Expertise: Liberty Characterization {CCS, CLDM} and Quality Assurance

Onchip variation models {AOCV ,LVF}

ANSYS Redhawk Apache Power Library {CDEV, PWCDEV, SPCURRENT}

Stdcells Library Design and Validation

Leadership Attribute: Situational and Servant Leadership

Team Management and cross functional collaboration

Publications

 

  • Frequency band widening technique for piezoelectric energy scavenger using non-uniform load distributionFrequency band widening technique for piezoelectric energy scavenger using non-uniform load distribution

Presented at ISSS 2017 held at IISc Bangalore · Jul 7, 2017 

  • Copper Electrodes Based Energy Harvester

 2016 IEEE Students’ Technology Symposium (TechSym) · Oct 2, 2016 

  • Frequency band widening technique for cantilever-based vibrartion energy harvesters through dynamics of fluid motionFrequency band widening technique for cantilever-based vibrartion energy harvesters through dynamics of fluid motion

Materials Science for Energy Technologies Volume 1, Issue 1, June 2018 

Quote

There is a powerful driving force inside every human being that, once unleashed, can make any vision, dream, or desire a reality.
Tony Robbins

Timeline

Senior Engineer , DEG Design

Micron Technology
09.2019 - Current

Stdcells Characterization Engineer

Soctronics Technologies
01.2018 - 09.2019

Engineer Trainee - Custom Layout Design

VEDA IIT

Master in Technology - VLSI Design

Ramdeobaba College of Engineering And Management,

Bachelor in Engineering - Electronics And Telecommunication

Shri Sant Gajanan Maharaj College of Engineering A

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