POORNIMAA
Chennai
Summary
Dynamic Project Lead with extensive experience at Mobiveil Technologies, excelling in RTL design and CXL protocol development. Proven track record in mentoring teams and enhancing project outcomes. Adept in Verilog programming and problem-solving, driving successful implementations and fostering collaboration to achieve high-performance results.
Overview
8
8
years of professional experience
Work History
Project Lead - Design
Mobiveil Technologies
Chennai
04.2024 - Current
- Initiated work on UMMC protocol, aligning development with customer specifications.
- Updated RTL components for PHY level per client requirements.
- Mentored junior team members to enhance project execution and skills.
Staff Engineer
Marvell Technologies
06.2022 - Current
- Led development of CXL TL Layer, upgraded from version 2.0 to 3.0.
- Completed implementation for all register blocks and enhanced error handling for CXL 2.0.
- Conducted CV testing for CXL IP controller in compliance with consortium standards.
- Validated RTL through simulation for CPI and GPI interfaces of TL Layer.
- Generated bit files for FPGA configurations and performed onboard testing.
- Enhanced RTL design, increasing data path from 128 bits to 256 bits in RAB.
- Acquired knowledge on CXL protocol concepts and analyzed design for CXL 1.1 generation.
- Managed configurations of CXL protocol concerning CPI specifications.
Senior Engineer
Mobiveil Technologies
06.2018 - 06.2022
- Executed design tasks for IP, including synchronous FIFOs, asynchronous FIFOs, and ALUs.
- Acquired expertise in Verilog from Samir Palnitkar's authoritative text.
- Utilized Cadence Design Compiler and lint tools to enhance design accuracy.
- Gained foundational knowledge of digital design concepts and Verilog programming.
- Studied RapidIO protocol and implemented it in a project.
Intern
Mobiveil Technologies
01.2018 - 06.2018
- Executed various IP design tasks including synchronous FIFOs, asynchronous FIFOs, and ALUs.
Acquired knowledge of Verilog through Samir Palnitkar's book for enhanced design capabilities.
Learned design tools including Cadence Design Compiler, lint, and CDC tools to streamline processes.
Gained foundational understanding of digital design concepts and Verilog language applications.
Studied RapidIO protocol to broaden expertise in high-performance communication systems.
Education
Bachelor of Engineering - Electrical, Electronics And Communications Engineering
PSNA College of Engineering And Technology
Dindigul04-2018
Skills
- Logical thinking
- CXL protocol
- RTL design
- Digital design
- Mentoring
- Teamwork
- Problem solving
- Adaptability
- Leadership
- Communication
- Time management
- Hard work
- IP design
- Synthesis
- Verilog programming
- PCI-Express TL layer
- RapidIO
- APB protocol
- AXI (RAB level)
- Digital design concepts
- Lint analysis
- CDC verification
- Vivado tools
- Trace analyzer (LeCroy)
- Synthesis guidelines
Accomplishments
- Star Performer Award: Received the Star Performer Award for providing maximum support to the CXL Protocol at Mobiveil Technologies.
- Star of the Quarter: Awarded Star of the Quarter for taking ownership of more blocks in CXL and consistently providing full effort as a Junior Engineer.
Timeline
Project Lead - Design
Mobiveil Technologies
04.2024 - Current
Staff Engineer
Marvell Technologies
06.2022 - Current
Senior Engineer
Mobiveil Technologies
06.2018 - 06.2022
Intern
Mobiveil Technologies
01.2018 - 06.2018
Bachelor of Engineering - Electrical, Electronics And Communications Engineering
PSNA College of Engineering And Technology