Summary
Overview
Work History
Education
Skills
Projects
Timeline
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JOEPRABHU

JOEPRABHU

Tamilnadu, Chennai

Summary

To ensure the development of high-quality, secure, and efficient software by leveraging tools like Coverity, Cpplint, and Valgrind, and following the Software Assurance Maturity Model (SAM)

4.0 years of experience in IP-level functional verification. As an accomplished IP Level Functional Verification Engineer, I specialize in verifying complex semiconductor IP cores, ensuring high-quality, robust, and reliable designs. With a strong foundation in digital design and verification methodologies, I bring extensive experience in creating and executing comprehensive test plans covering various scenarios and edge cases.

Overview

4
4
years of professional experience

Work History

Design Engineer

SVP2 Migration (SSIR Bangalore)
06.2024 - Current
  • To ensure the development of high-quality, secure, and efficient software by leveraging tools like Coverity, Cpplint, and Valgrind, and following the Software Assurance Maturity Model (SAM)
  • Designed and developed software applications to meet business requirements and quality standards
  • Performed static code analysis using Coverity to detect software defects and vulnerabilities in early stages of development
  • Analyzed Covert scan results, prioritizing issues by severity and collaborating with developers to fix defects.
  • Integrated Coverity into the CI/CD pipeline for continuous monitoring and reporting
  • Apply Cpplint to enforce coding style and standards, particularly for C++ codebases
  • Reviewed and resolved Cpplint issues to ensure consistent and readable codebase
  • Implement practices and processes from the Software Assurance Maturity Model (SAM) to enhance software security
  • Conduct threat modelling, security testing, and risk assessment to identify and mitigate potential security risks.

Design Verification Engineer

Mobiveil Technologies (India) Private Limited
09.2021 - 06.2024
  • Verification of non-volatile Memory express(NVMe)
  • Verified basic test case failures for the 256 DBW in collaboration with team members.
  • Verified and debugged feature failures on DBW of 256 by working on deleting the sq scenario.
  • Worked on end-to-end fields to verify the feature and debugged DBW failures on 256.
  • Contributed to the development and testing of the Abrupt Shutdown feature
  • Verification of Enterprise Flash Controller(EFC)
  • Created test plans and implemented features for SINOCHIP customer requirements, ensuring compliance with quality standards.
  • Verified features for CDNS and MV_PHY, as well as debugged any failures
  • Verified YMTC configuration for Timing Modes 5 and 21, incorporating enhancements for data widths of 16 and 32.
  • Worked on Coverage work for YMTC customer.
  • Developed and implemented complete RAL for EFC.
  • Implemented Timing mode 22 support for AVERY.
  • Verified the Micron Model with all test cases at Timing Modes 0 and 5
  • Verified Toshiba Model against appropriate test cases during Timing Mode0.
  • Verification of xSPI – AXI4 NOR Flash Controller
  • Developed test sequences and cases to validate command usage in MicronX4, Semper, and Cypress memory models.
  • Resolved error in existing BFM for optimal functionality
  • Developed test cases for enhanced code coverage
  • Verified PSRAM/HyperRAM Controller using AXI Interface
  • Created comprehensive test plan and test cases to validate functionality, focusing on corner scenarios.
  • Verified an APB I2C Bridge using UVM methodology.
  • Successfully established operational environment from the ground up
  • Developed and executed write and read test cases for APB & I2C protocols
  • Repeated write and read test cases in I2C.

RTL Design Engineer

QualiTi Systems pvt ltd
01.2021 - 08.2021
  • Designed and implemented visually appealing window resolutions for applications
  • Developed and implemented optimal window resolutions to enhance user visual experience
  • Ensured compatibility across various display types and sizes, such as desktop monitors, laptops, tablets, and smartphones
  • Collaborated with UI/UX designers to develop visually consistent and responsive interfaces across various resolutions
  • Conducting tests to ensure proper application rendering across various resolutions and aspect ratios
  • Identify and resolve issues concerning display quality, scaling, and performance.
  • Optimize graphics and rendering processes to ensure smooth performance without compromising visual quality.

Education

Skills

  • Verilog
  • System Verilog
  • UVM
  • Cadence Xcelium 2009
  • Mentor Questasim 107
  • Synopsys VCS
  • ONFI 51
  • Nvm-Express
  • AMBA APB
  • I2C
  • AMBA AXI4
  • UART
  • Windows
  • Linux
  • Perl

Projects

SVP2 Migration (SSIR Bangalore), 06/2024 - Present, Design Engineer, To ensure the development of high-quality, secure, and efficient software by leveraging tools like Coverity, Cpplint, and Valgrind, and following the Software Assurance Maturity Model (SAM), Participate in designing and developing software applications that meet business requirements and quality standards., Utilize Coverity to perform static code analysis to detect software defects and vulnerabilities early in the development process., Analyze results from Coverity scans, prioritize issues based on severity, and collaborate with developers to remediate defects., Integrate Coverity into the CI/CD pipeline to ensure continuous monitoring and reporting., Apply Cpplint to enforce coding style and standards, particularly for C++ codebases., Review and resolve Cpplint issues to maintain consistency and readability across the codebase, Implement practices and processes from the Software Assurance Maturity Model (SAM) to enhance software security., Conduct threat modeling, security testing, and risk assessment to identify and mitigate potential security risks Mobiveil Technologies (India) Private Limited, 09/2021 - 06/2024, Design verification engineer, Verification of non-volatile Memory express(NVMe), Verified the basic test case failures for the DBW of 256., Worked on deleting the sq scenario to verify the feature and debugged the failures on DBW of 256., Worked on E2E fields for verifying the feature and debugged the failures on DBW of 256., Worked on the Abrupt shutdown feature and verified the failure., Verification of Enterprise Flash Controller(EFC), Developed the test plan and implementation of features for SINOCHIP customer requirement and verified., Verified the features for CDNS and MV_PHY and debugged the failures., Verified the YMTC configuration with Timing Mode 5,21 along with 16&32 data width enhancement., Worked on Coverage work for YMTC customer., Developed RAL complete implementation for EFC., Added the Timing mode 22 support for AVERY., Verified the Micron Model with all test cases at Timing Mode 0&5., Verified the Toshiba Model with all test cases at Timing Mode0., Verification of xSPI – AXI4 NOR Flash Controller, Developed sequences and test cases to verify the commands used in MicronX4, Semper and Cypress memory model., Resolved error in existing BFM to function properly., Developed test cases to improve code coverage., Verification of PSRAM/HyperRAM Controller with AXI Interface, Developed test plan and test cases to hit corner scenarios for verify the functionality., UVM Based verification of APB I2C Bridge, Build environment from scratch., Basic write and read test cases in both APB & I2C., Repeated write and read test cases in I2C. QualiTi Systems pvt ltd, 01/2021 - 08/2021, RTL design engineer, To design, implement, and optimize window resolutions for applications, ensuring that the user interface is visually appealing and functions effectively across various devices and screen sizes., Develop and implement window resolutions that provide the best visual experience for users., Ensure compatibility across different display types and sizes, including desktop monitors, laptops, tablets, and smartphones, Collaborate with UI/UX designers to create interfaces that are visually consistent and responsive to different resolutions., Conduct testing to ensure applications render correctly across different resolutions and aspect ratios., Identify and resolve any issues related to display quality, scaling, and performance., Optimize graphics and rendering processes to ensure smooth performance without compromising visual quality

Timeline

Design Engineer

SVP2 Migration (SSIR Bangalore)
06.2024 - Current

Design Verification Engineer

Mobiveil Technologies (India) Private Limited
09.2021 - 06.2024

RTL Design Engineer

QualiTi Systems pvt ltd
01.2021 - 08.2021

JOEPRABHU