PRAMOD KUMAR P M

Professional with 18 years of experience providing layout design for RF, analog, and mixed signals in VLSI. Forward-looking leader with a sound understanding of layout design, and the ability to think laterally to provide solutions. Also, I have experience in PnR and handling interfaces between analog and digital in SOC.

_____________________________________________

TIA

Nodes : GF- BiCmos 130n ,90n

Team of 15

 Led and Taped out 3 Chips @ frequency range of 100 200G & 400G.Handled Multiple roles like owning up Digital Macro, Package support, also provided multiple solutions for highly challenging Floorplan and Design requirements.

_____________________________________________

Phase detector and cross-domain clocking module

Node : SF4(FF)

Came up with a flow wherein the floorplan will be built in Virtuoso, and the DB will be taken to Innovus for digital closure. This had tighter slew and skew requirements

_____________________________________________

MODEL Test chip

Node : Samsung 4nm

Team of 12 

Lead a test chip to evaluate the device models

_____________________________________________

SOC ANA-DIG Interface

Node : SF4(FF)

Owned the interface section ,setup a flow for extraction views which are compatible for both Analog and Digital simulation

TSMC16ff

Team of 4 

Owned Interface section between Analog top and Digital Top in an SOC Came up with the Hybrid solution for timing closure also owned up PnR part of DAC digital scrambler which operates at 2p5G clock.

_____________________________________________

RF TX TOP((3G/5G)

Node : UMC14ff

Team of 6 

Owned IP Top level Layout of TX and monitored DAC/RF part of the TX TOP. R2R DAC, AAC filter followed by RF driver out

_____________________________________________

ADC

Node : TSMC16ff

Team of 4

Owned ADC TOP for RX path 56 ADC slices of 1G working at different phases of 14G clock. Also Built the Layout for Frontend part of the ADC (Clocking and Data path)

_____________________________________________

BUCK Converter

Node : KF 180nm

Team of 8

Taped out the BUCK converter Chip with 4 Versions – 30A,20A ,12A and 6A.Was part of the debug team on substrate isolation study.

_____________________________________________

IP: LO QUADGEN

Node : UMC28

Inductor based design QUADGEN designed for 6G-24G data.It had three paths div2/div4 and div8 .

_____________________________________________

Power Management- Power path , Charger LDOs Bandgaps

Node : GF 180nm.

Handled layout for Power path section (USB, Adapter and Battery path) of the, This Chip which had current rating of 2A .Also Handled Charger and LDOs section of the same chip.

Handled entire PnR flow for 3Mhz Digital Design in Power Management Chip (GF180nm process) did Static Timing Analysis, timing closure. MMMC and QRC based STA.

_____________________________________________

• Planned work schedules are based on individual strengths, weaknesses, and job requirements
• Monitored progress on projects, providing feedback and support as needed also managed resources and delegated tasks to ensure timely completion of projects.
• Conducted regular performance reviews with team members, providing constructive criticism when necessary.
• Provided assistance with conflict resolution among team members.
• Implemented strategies designed to improve efficiency across multiple departments, collaborated with cross-functional teams to develop strategies
• Participated in the hiring process, identifying and selecting candidates who fit the team’s needs and the company culture

• Father's Name: Manikantan Nair KP
• Date of Birth: 08/09/1986
• Nationality: India
• Marital Status: Married

I hereby declare that the information furnished above is true to the best of my knowledge.