Prasanth Devalapalli

Project : Mahua (DDR team)

Client : Qualcomm

HM’s : HSC_NOC_MSOUTH_LEFT

Inst Count : 4.6 Million with 4 macros

Layers : 15

Technology : TSMC 3nm technology

Ports : 54k

Frequency : 1.24ghz

Role : PnR.

Tools : Innovus

Duration : 2024 SEP to 2025 APR

Challenges :

1.Involved in multiple floorplan experiments to converge place congestion and timing.

2. Here I have FT ( 15K feed through ) ports because of ft’s buffering I saw huge congestion and tried multiple experiments to reduce the hotspots in sequential manner.

3.Timing was bad for few paths applied weightage effort high and created path groups so that I got better improvement.

4.Since there is huge inst count and hotspots facing so many shorts and DRC's where we have tried many experiments to get it reduced.

5.In ECO phase due to less space availabilty as utilization reached more than 60% after route stage faced a lot of issue in adding new cells for timing convergence, signoff activities and reducing crosstalk, noise , maxcap, maxtran.

6. Manually routed lot of nets in higher layers due to high crosstalk, noise and bad nets where routed in lower layers

7. Involved in closing all the signoff checks like PV, PDN, FV and CLP.

Project : Mahua (DDR team completely worked on FLOORPLAN ACTIVITY )

Client : Qualcomm

HM’s : HSC_NOC_MSOUTH_LEFT, HSCNOC_MSLICEHM0

Inst Count : 2.8 Million with 45 macros

Layers : 15

Technology : TSMC 3nm technology

Ports : 30K

Role : FLOORPLAN

Tools : Innovus .

Duration : sep 2024 to nov 2024

Challenges :

1.Involved in multiple floorplan experiments to converge place congestion and timing.

2.Because of macro count seeing high congestion in between macros channels.

3.Cleaning CI checker (TCIC checks) is very critical for this hm where lot of rules to be followed in order to get clean floorplan.

4.Most of the memories were abutted because of abutment seeing high net lengths so that timing is going bad.

5.Involved in signoff activities like PDN, CLP, FV and PV for floorplan closure.

Project : Bonito (DDR team)

Client : Qualcomm

HM’s : hm_monaq_channel_tile

Inst Count : 500k

Layers : 12

Technology : TSMC 4nm

Ports : 8k

Role : Floorplan & PnR

Tools : Innovus

Duration : Jan 2024 to sep 2024

Challenges :

1.Handled one channel tile with no macros and huge FT dominated block with 8K where Congestion , crosstalk , noise and all DRV, DRC issues are difficult to close them.

2.As there are more FT's lot of customized FT buffering done horizontally where we have faced unavailability of horizontal resources and found lot of cross talk and noise due to parallel running of the nets in same layers.

3. Tried resolving them using higher layers and higher drive strength cells to overcome them.

4. There are lot of timing failures of these FT paths due to strict budget issues given.

5. Involved in closure of all signoff activities and in BTO struggled in closure of DRV's.

6. Also in parallel worked on other Hm's on signoff closures and in absence of other Hm owners

• Overview: 7nm, single voltage block.
• TOOLS: Synopsys Fusion Compiler, Synopsys Prime Time
• SCRIPTING LANGUAGE: TCL, Unix
• Client: INTEL
• Worked on block with 1.0GHz frequency, single Voltage Domain with no macros.
• Executed the PNR activities of the block which was critical in terms of shorts and congestion.
• Tried different experiments for reducing the shorts at the notch area.
• For the congestion reduction tried various experiments using partial blockage and checker board blockage, keep-out margin etc.
• Tried path group setting, clock push and pull, bound creation etc. has been tried for meeting the timing.
• Performed the sign-off checks for the block.

• Overview: 7nm, single voltage block.
• TOOLS: Synopsys Fusion Compiler, Synopsys Prime Time
• SCRIPTING LANGUAGE: TCL, Unix
• Client: INTEL
• Worked on block with 1.0GHz frequency, Macro dominated block with count 83, single Voltage Domain.
• Worked on block level place and route. Responsibilities included Project setup, Floorplan, placement, clock tree generation, routing, Static timing analysis, and partition level DRC, and LVS.
• Multiple experiments have been tried for floorplan and blockages has been added based on shorts and congestion analysis.
• CCD is enabled and clock pull push is done to meet timing at SS level and maintained 70:30 cell to net delay ratio.
• Executed and analyzed sign-off checks like STA_PT, Caliber, VCLP, FEV and RV.
• Performed many ECO iterations to reduce shorts, legalized cell placements, routing manually for different timing closures with iterations of LVS and DRCs fixes.

• Acquired knowledge of ASIC PD flow from Floorplan to GDSII along with various inputs at each stage.
• Hands on experience in Floorplan, Power plan, Placement, CTS, Routing in 40nm technology.
• Worked on floorplan with high utilization and ensuring good contiguous core area for std cells.
• Analyzed and understood the reports of each stage in the PNR tool.
• Hands on experience in industry standard EDA tools - Synopsys IC Compiler II and Prime Time.

• Around 3 years of experience in Analysis, Design, Development, Implementation, Integration and Testing of Core Banking Application (FINACLE - Core Banking Solution by Infosys Technologies Ltd) for different banks.
• Client: DISCOVER Bank (US)
• Tools: Finacle 10x, Finacle 7x, Oracle 10g, SecureCRT, ServiceNow.
• Challenges: Maintenance and customization related to the code of CBS (Core Banking Solution) responsible for Credit Bureau Reporting.
• Working on Agile Methodology and delivering the requirements as per business requirement.
• Coordinating with Onsite for requirement gathering and POC's.
• Working with business team to develop regression models in SAS to ensure the correctness of reporting whenever any code change is happening in the CBR.