Prateek Mukherjee

Innovative professional in computer hardware engineering known for high productivity and efficient task completion. Possess specialized skills in circuit design, system testing, and hardware troubleshooting which ensure top performance in developing and enhancing computing solutions. Excel in problem-solving, communication, and teamwork, crucial for success in collaborative projects and driving advancements in technology.

• Grouping-Based Channel Estimation Scheme for IRS-Assisted Wireless Communications Network, IEEE Communication Letters
• Single Anchor-Aided Channel Estimation Strategy for IRS-Based Wireless Communication Systems, IEEE-SPCOM 2024
• Mobile Molecular Communication with Relay Assisted Network Coding: Framework and Analysis, IEEE VTC-2024

Best Graduating Student Award | EEE Department, 11/01/23

1)   OPAMP design

• Designed a folded cascode OPAMP and accompanying current mirror biasing circuitry.
• Achieved voltage gain of 70 dB and UGB of 80kHz.
• Designed a full CMOS, 4-fingered implementation of a XOR gate that operates at 500MHz, on Microwind.

2)   Development of a novel QC-LDPC decoder

• Coded the LDPC decoder architecture on Verilog and tested it for functionality on Modelsim
• Synthesized the architecture on Zedboard zcu-106 and reported an 81.26% gain in circuit utilization as compared to the previous approach.

3)   IRS assisted 6G communication

• Proposed a channel estimation scheme that is based on grouping of the elements in IRS. This approach drastically reduces the pilot overhead and increases the achievable rate. The work has been accepted in IEEE Communication Letters journal.
• Received funding of Rs.30000 from university to develop a working prototype of the IRS.