Prateek Pandey

Proj: 12.3MP Rolling Shutter Image Sensor for surveillance

Role: Chip Lead

- Handling the in and out of design, layout, physical development, testing and characterizing of 12MP part.

- Designed a push pull low area precharge buffer for a 2.5nF load with a settling of less than 150ns across corners.

- Came up with a technique using just a switched cap (20fF) to discharge a high capacitive load quickly.

-Ramping up the juniors to get versed with image sensor operation and to take up challenging stuff.

- Main challenges include shrink in row time and increase in the RC load.

Proj: 8MP Rolling Shutter for surveillance

Role: Analog Lead

- Took the ownership of Analog blocks including floor planning, area-estimation, speed and power calculations.

- Design of Hi and Lo booster charge pumps to support load of 8MP and meet the 60fps linear speed and 30fps for 3exp HDR.

- Designed pixel power regulator to ensure minimum row noise due to power supply of pixels.

- Block and top level functional and performance level simulations.

- Contributed in post-silicon tuning to make sure the read noise is 1e- at max column-amp gain.

Proj: 2.3MP Global Shutter Image Sensor for scanning and AR/VR applications

Role: Analog Lead

- Took the ownership of Analog blocks including floor planning, area-estimation, speed and power calculations.

- Sense amplifier based column memory to flush out 8 column data in 1 clock cycle to digital.

- Design of Hi and Lo booster charge pumps to support load of 2MP and meet the 120fps speed.

- I was sent to US twice to assist test engineers for carrying out validation activities on time.

- Contributed in post-silicon tuning to make sure the part reaches mass production.

Responsibilities:

- Developing critical blocks like Buck/Boost converters using Verilog-AMS followed by testbench to verify the functionality and performance for the same.

- Designing bias circuits/reference in the above project in TSMC 110nm technology.

- Characterizing various low-VT, high-VT devices to extract maximum performance from available devices for 110nm technology.

- Designed 65dB gain telescopic amplifier for 1st stage of Pipeline ADC (internal project).

- Designed low resistance (0.3ohms), timer based P-type power switch to avoid huge inrush current to the load.

- Learned Perl scripting to create ADE-L type of environment for internal use.

- Development and Verification of a tool which will ensure an extensive coverage of IPs across PVT and MC sim.