Pratik Kumar

RTL2GDSII, VLSI EXPERT - JUN-JUL 2024

• 5 Stage Pipelined Processor Feb - May 2023 :- Created a 5-stage pipelined MIPS Processor in Verilog using Xilinx Vivado which include Hazard detection and correction with forward mechanisms.
• Design an Asynchronous FIFO, Apr - Apr 2023 :- Designed a 16x8 Asynchronous FIFO (First-In-First-Out) memory to facilitate data transfer between two asynchronous systems.
• Sequence detector, Aug - Aug 2023 :- Design a double sequence detector circuit to detect the patterns "0010" and "0001" using a Mealy machine architecture. Simulate the RTL design to verify its correctness and functionality and implement the design on Zedboard FPGA using Vivado's implementation tools
• SPI Protocol in Verilog and verifying its functionality, Sep - Oct 2023 :- Designed a Serial Peripheral Interface (SPI) interface that can enable SPI write operation based on Verilog. We use simulation to confirm that this concept works as intended.
• Synthesis of Adders, Oct - Oct 2023 :- Synthesis of parameterized N-bit Carry Look-Ahead Adder, Carry Increment Adder, and Carry Select Adder on Cadence Genus Synthesis Solution Tool using standard cell library at 45nm technology. Analyzed their Relative Performance Speed, Area and Power Consumption for different bit widths (N).
• Design and Layout of 2-bit Ripple Carry Adder, Nov - Nov 2022 :- 2-bit Ripple Carry Adder Schematic and Layout using Cadence Virtuoso Layout Suite using gpdk 45nm library.

• Digital Electronic,VLSI Architecture,VLSI Design,Physical Design,Clock Domain Crossing,Static Timing Analysis,CMOS Inverter

·  4-bit ALU Development: Designed and implemented a 4-bit ALU using Verilog HDL, incorporating Full Adder and Full Subtractor for key arithmetic operations.

·  RTL2GDSII Flow: Managed the entire RTL to GDSII flow, employing Synopsys tools for synthesis, optimization, and timing analysis to ensure successful design implementation.

· Functional Verification: Executed comprehensive verification of the ALU design, using Synopsys VCS for simulation and VCS Verdi for waveform analysis.

Physical Design: Executed tasks including floor planning, placement, clock tree synthesis, and routing, ensuring successful final verification with testbenches