Praveen Pai
System Electrical Engineering
Bangalore
Summary
Experienced tech industry leader with nearly 20 years of expertise in delivering platform electrical solutions for a range of products, including mobile platforms, desktops, and HPC AI server systems. Proven ability to engage with customers to address challenges and offer effective solutions. Skilled in integrating third-party IPs into product designs and managing supplier relationships. Passionate about fostering a culture of innovation, ramping teams and developing future leaders, with a coaching mindset (ICF ACC-PCC training). Proven expertise in building high-performing teams and delivering successful solutions for semiconductor products.
Overview
20
20
years of professional experience
6
6
years of post-secondary education
Work History
Director Electrical & Org Development
FlexAI India Pvt Ltd
04.2024 - Current
- Delivered the electrical architecture solution for FlexAI's first HPC AI product concept, based on a chiplet architecture (a novel optimized solution designed to work alongside the NVIDIA H100/B200 and other similar products).
- Led a team of 6 during the architecture phase and took ownership of the entire electrical solution space, including SI, PI, PD, rack server PD design, and the selection of third-party IPs for IOs (SerDes/PCIe). Filed a patent alongside 4 team members for a novel hardware link that enables scalable compute at the motherboard level. Key Interfaces: SerDes 224G, PCIE Gen6.0, 32Gbps D2D, HBM4.0, UCIe 2.0.
- Developed a custom vertical power delivery (VPD) solution to align with the FlexAI architecture by collaborating with Vicor technical team through bi-weekly meetings over a quarter. Selected AlphawaveSemi's IP (SerDes/PCIe combo) as the preferred solution following discussions with their customer-facing team.
- Delivered SI channel solution for our custom D2D configuration at 24Gbps in ADS Tool. A SOW was agreed upon and signed to finalize the activity to run with actual buffer models of the D2D IP provider (Bluecheetah).
- Gained experience in server rack PD design while collaborating with the Legrand technical team, focusing on the 42RU standard rack solution.
- Provided financial projections for team growth and skill development, collaborating with the India site MD to integrate data into the company's financial model.
- Drove seamless collaboration between global teams across India, the US, and Europe. The hardware team (India) and software team (Europe) worked in close coordination to deliver the first architectural feasibility analysis for the FlexAI HPC AI product. Got recognition from the CTO for my efforts.
- Identified skill gaps within the organization and established an effective hiring process to support strategic growth and talent acquisition.
Director - Marketing & Customer Engineering
Infinipack Pvt Ltd
10.2023 - 03.2024
- Responsibilities included analyzing market trends, identifying potential customers, establishing company culture, hiring/managing talent and leading the team on platform architecture and design [SI/PI].
- Collaborated closely with the CEO and COO to create a comprehensive pitch deck, aligning key business strategies and goals, and effectively communicating the company's vision to potential investors and stakeholders.
- Engaged with potential customers, partners, and investors, gaining valuable insights into the advanced packaging ecosystem in India.
- Recruited and onboarded a total of 8 junior engineers (4 interns), providing mentorship and training to help them quickly ramp up and gain proficiency in key concepts and industry practices.
Analog Engineering Manager
Intel India Pvt Ltd
06.2021 - 09.2023
- Led the package electrical (SI/PI) team of 10 in delivering next-generation graphics packaging solutions for discrete client products, server products, and the automotive segment.
- Successfully delivered electrical solutions for discrete graphics card (Intel Arc series), HPC products (Rialto Bridge and next gen, successors of Ponte Vecchio), and automotive segment.
- Built and grew a new team by hiring both fresh and experienced candidates, trained them on methodology and processes, and successfully delivered electrical solutions for packaging.
- The team demonstrated strong credibility, ownership, and excellent stakeholder relationships.
- Filed 5 patents as part of an innovation drive and led the automation initiatives to enhance execution flow and improve efficiency.
- Acted as a coach, fostering ownership and accountability in team members, creating a culture of continuous learning.
- Delivered a 10-day Personal Leadership Workshop, earning the DRA award.
- Earned ICF ACC-PCC certification, utilizing leadership coaching to drive performance.
Platform PI IO Architect
Intel India Pvt Ltd
04.2018 - 05.2021
- Delivered package PI solutions for next-gen Intel and third-party IPs, while supporting customers in adopting new technologies that extend beyond Intel platform guidelines. Products: Comet Lake, Rocket Lake, Meteor Lake.
- Led the development of novel PI solutions using new technologies for upcoming market segments. This role involved collaborating with technology groups to enable new package designs and die solutions, working with third-party IP vendors to integrate their solutions into Intel SOCs, and influencing the HSIO feature set for next-gen Intel platforms.
- Developed a novel methodology to optimize the PI noise specification for the next-gen HSIO [PCIE Gen4.0], reducing the PI BOM and overall package cost, earning a Group Recognition Award for the effort. This work was published as a paper at the SHS2020 conference.
- Directed the identification, creation, and closure of SOWs for the electrical domain with third-party IP vendors.
Platform HW Lead (Client Customer Engineering)
Intel India Pvt Ltd
12.2015 - 04.2018
- Offered extensive customer design support for over 100 OEM/ODM designs, from the initial design phase through to PRQ. Products: Kaby Lake, Coffee Lake, Coffee Lake-R.
- Provided platform hardware collaterals (RVP/PDG/Tutorials) to support all customer designs.
- Spearheaded customer workshops and resolved design gaps in the PDG, enabling faster development and successful platform adoption.
- Served as the single point of contact for all platform hardware-related customer issues, quickly identifying root causes and leading task forces to resolve them within one week. I addressed design gaps, clarified PDG recommendations, and resolved mismatches in RVP schematics/PDG, ensuring efficient communication and issue resolution through weekly customer updates.
- Influenced the RVP [Reference Validation Platform] landing zone to align with popular customer configurations, creating a new reference kit that integrated key design elements to help customers reduce development time by leveraging optimized, emerging market designs.
- Worked closely with customers to promote the adoption of Intel reference collaterals, leading a team of 5 to develop customized designs (Modular Core Design) that minimized design variations and streamlined issue resolution.
Platform SI/PI Lead
Intel India Pvt Ltd
03.2015 - 12.2015
- Delivered a comprehensive platform SI/PI solution for a unique reference design based on the Atom SOC Bay Trail.
- Designed platform electrical [SI/PI] solution for a two-board FFD, enabling customers to replicate the core board and customize the I/O board. The design, powered on successfully in 12 weeks.
- The core and IO boards were interfaced at two locations using an 80-pin connector. I optimized connector placement for clean IO routing, considering interface routing, length, speed, connector frequency, and power layout between the boards.
- Traveled to Taiwan to collaborate directly with Wistron. Developed a complete system design for Intel Atom SOC, optimizing PD and SI solutions, reducing motherboard stackup layers from 6L to 4L and providing cost savings of $1.75 per platform.
Platform PnP Engineer
Intel India Pvt Ltd
06.2014 - 03.2015
- Optimized Power KPI and VR efficiency for Intel's first Tablet product, based on Atom SOC Bay Trail.
- Analyzed the Tablet Idle power KPI weekly with the latest BKC (BIOS/OS), monitoring for any regressions.
- Proposed novel way to measure VR efficiency during idle scenario using dynamic current profiles, resulting in a 150mW power savings when PMIC efficiency improved from 82% to 85%. This analysis, shared with the PMIC design team, highlighted the efficiency gain, though it also identified potential cost implications for altering the PMIC design.
Power Integrity and Signal Integrity Engineer
Intel India Pvt Ltd
08.2005 - 06.2014
- Led display interface design for Intel tablets (DP1.2, eDP1.4a, HDMI1.4), delivering 4K resolution support.
- Innovated display validation methodology, eye measurement using DPOJET, presented at DTTC conference.
- Delivered signal integrity solutions for MIPI HSI/HSIC (High-Speed Synchronous Interface/High-Speed InterChip) interfaces.
- Designed IO [DDR3 1600/DDR4 2133/PCIE Gen3.0] CPU Package PD network for Intel CPU chipsets.
- Validated the Intel chipset [MCH] to ensure it met the PD noise requirements across all PD rails [CORE/FSB/DDR/PEG/LVDS] in the lab using high-end gigahertz oscilloscopes [Tektronix/Agilent].
- Correlated the impedance profile between measured data and simulation data using a VNA.
- Received the Division Impact Award (DIA) and Division Recognition Award (DRA) for delivering optimized solutions that resulted in substantial cost savings.
Education
M.A.Sc. - CAD for VLSI
Carleton University
01.2003 - 08.2004
B.E. - Electronics and Communications
Manipal Institute of Technology
08.1998 - 08.2002
Skills
Problem-solving
People management
Strategic planning
Organizational development
Leadership development
Teamwork and collaboration
Coaching and mentoring
Awards
- Group Recognition Award, Q2 2020, For delivering Rocket Lake PCIe gen 4 capability with reduced package and platform costs without sacrificing performance
- Division Recognition Award, Q2 2020, For Power Integrity DCR (Power Bot 1.0) and PDC automation tool to enable faster and efficient design reviews and signoff for RVP/AEP/BEP platforms
- Division Recognition Award, Q4 2007, In recognition for development of the Hybrid Bump Pattern which enabled substrate cost reduction for Cantiga and future Chipset projects, saving $57M on Cantiga alone
- Division Impact Award, 2007, In recognition of your outstanding risk taking and effort to hit the stretch goal of 396mils Cantiga CR size
Patents Publications Awards
- Color Mutant Capacitors, D149124-US, Praveen Basty Pai, Vikas Rao, Parthasarathy Ramaswamy
- An effective methodology to enable low cost system design for next Gen High Speed IO's, SHS2020, Pankhuri, Raj Mohan Mondal, Praveen B Pai, Ashwini Anil Kumar
- Achieving robust Power Integrity Solution while Integrating multiple IPs, DesignCon, 01/01/20, Praveen Pai, Vishram Pandit, Lokender Singh, Geetha Vanga
- A novel methodology to handle the layout constraints for designing an optimal Power Delivery Network, DesignCon, 02/01/09, Praveen Pai, Parthasarathy Ramaswamy, Julius Delino
Timeline
Director Electrical & Org Development
FlexAI India Pvt Ltd
04.2024 - Current
Director - Marketing & Customer Engineering
Infinipack Pvt Ltd
10.2023 - 03.2024
Analog Engineering Manager
Intel India Pvt Ltd
06.2021 - 09.2023
Platform PI IO Architect
Intel India Pvt Ltd
04.2018 - 05.2021
Platform HW Lead (Client Customer Engineering)
Intel India Pvt Ltd
12.2015 - 04.2018
Platform SI/PI Lead
Intel India Pvt Ltd
03.2015 - 12.2015
Platform PnP Engineer
Intel India Pvt Ltd
06.2014 - 03.2015
Power Integrity and Signal Integrity Engineer
Intel India Pvt Ltd
08.2005 - 06.2014
M.A.Sc. - CAD for VLSI
Carleton University
01.2003 - 08.2004
B.E. - Electronics and Communications
Manipal Institute of Technology
08.1998 - 08.2002
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