Praveenkumar Hallur
Bengaluru
Summary
Dynamic Verification Manager with a proven track record at TESSOLVE, excelling in technical team leadership and project management. Spearheaded SoC and IP verification projects, leveraging expertise in SV and UVM methodologies. Successfully mentored teams, achieving project goals. Adept at overcoming technical challenges and delivering high-quality results for global clients.
Overview
17
17
years of professional experience
Work History
Verification Manager
T&VS/TESSOLVE
10.2012 - Current
- Leading subsystem/IP verification team
- Technical team management
- Worked on SoC/Subsystem/IP
- Helping team on technical challenges
- Currently working on TI, US client
- Worked with reputed clients Infineon UK, NXP, Ericsson AB Sweden
Senior Verification Engineer
ADV TECHNOLOGIES
02.2012 - 10.2012
- Worked with cypress semiconductor client on GLS.
- Running regression on GLS on new derivative with test suite.
- Regression debug and sign-off.
Verification Engineer
L&T INFOTECH
01.2011 - 02.2012
- USB 3.0 IP Verification – coding test environment, test case, monitor, functional coverage.
- Running regression, debugging
- USB2.0 LPM Verification - Functional coverage analysis, test creation for coverage holes.
- BFM integration, ip integration.
Verification Engineer
Synopsys India Pvt Ltd
Bangalore
08.2008 - 12.2010
- USB2.0, UTMI LPM feature Verification – Coding TB Environment, tests, functional coverage, regression running and debug
- Verification of ADP and EH in serial mode - Coding TB Environment, tests, functional coverage, regression running and debug
- USB2.0 OTG Verification - Coding TB Environment, tests, functional coverage, regression running and debug
Education
M.Tech - VLSI & ES
Sri Jayachamarajendra College of Engineering
Mysore11-2007
B.E - E&C
Basaveshwar Engineering College
Bagalkote04-2004
Skills
- Technical team leadership
- Mentoring team members
- Project management
- Verilog HDL, SV, Vera
- Methodology - VMT, VMM, OVM, UVM
- Developed a Complete block level testbench
- Performed block level verification
- Performed SOC Verification
- Written a coverage and verification plan
- Sequence writing
- Test case development (Directed test cases)
- Test case development (Randomized test cases)
- Gate Level Simulation
- VIP development
- Monitor, Checkers & scoreboard development
- Test bench Automation (Scripting, regression)
- IC Validation Pre & Post Silicon
- Other Languages - C, C, C#, PERSPEC
- EDA Tools - Cadence - ncsim, Simvision
- Mentor Graphics – QuestaSim, ModelSim SE, VCS, ISE, Chipscope
- Synopsys – VCS, DVE, VERDI, CERTITUDE
- Protocols
- UTMI – USB20; ULPI – USB20; PIPE- USB30; I2C, JTAG
- Scripting - Shell, TCL, Perl
Timeline
Verification Manager
T&VS/TESSOLVE
10.2012 - Current
Senior Verification Engineer
ADV TECHNOLOGIES
02.2012 - 10.2012
Verification Engineer
L&T INFOTECH
01.2011 - 02.2012
Verification Engineer
Synopsys India Pvt Ltd
08.2008 - 12.2010
M.Tech - VLSI & ES
Sri Jayachamarajendra College of Engineering
B.E - E&C
Basaveshwar Engineering College