Pushkar Aravind Tawade
SoC Design Engineer
Bengaluru
Summary
- Total 14.5 Years of experience diversified across SoCs, IPs, Test Chips and FPGA Based Product Design with 8+ years in leadership role.
- Expertise in RTL Design and Execution, Micro-architecture Definition, TFM, Board Bring Up.
- Exposure to Verification Test Planning, Scripting (Perl, Python, Tcl, Shell)
Overview
15
15
years of professional experience
2014
2014
years of post-secondary education
Work History
SoC Logic Design Engineer
Intel
07.2022 - Current
- Led design reviews and provided critical feedback for continuous improvement in product quality.
Staff Engineer (SoC Design)
Qualcomm
12.2019 - 06.2022
- Successfully Taped Out 5 SoCs as TLMM and IO Design Lead
- Supervised TLMM and IO designs for all 5nm and 7nm SOC's executed out of multiple India Centers
- As a TLMM Lead, captured GPIO requirements from IPs, Subsystems, HW Platform designers, DFT Team and delivered specifications in co-ordination with SoC Chipsets Architects (HW and SW) including System Wake Up Interrupt requirements and Bit Bang signal planning.
- As a IO Design Lead, built specifications for suitable pad type selection, Pad Placement and Pad Order adhering to guidelines and meeting requirements from DFT, Floor-plan, Routing, Tiling and Package teams
- Responsible for development and delivery of quality RTL
Chief Engineer
Samsung Research India
10.2018 - 11.2019
- As a Logic Design Manager successfully delivered Active Distributed Antenna System (DAS), critical component for Samsung's indoor 5G solution, in a extremely short runway of 10 months
- Managed 12+ FPGA Engineer across Bangalore and Suwon(South Korea) sites, collectively responsible for RTL design, validation for all 3 FPGAs in system
- Owned System Level Register Definition, SW Programming Guide, HW Design Specifications along with Interface FPGA's Micro-Architecture and Top RTL Integration. This includes multiple complex IPs such as CPRI and 10G Sideband Interface, Chip to Chip, IQ Processor Block (IQ Compression, IQ Combiner, CPRI Mapper De-Mapper)
- Successfully led product bring up (including 3 FPGAs and Onboard Ethernet Switch IC) resulting in successful integrated 1st NR call testing with in-house DU and Third Party Antenna Units using ETM data.
Senior Lead Design Engineer
Cerium Systems
02.2016 - 09.2018
- Worked on Multiple project deliveries for Client Intel in ODC and on-site for DDRPHY IP and MIPI IP Design Team
- Primarily worked on VISA Network Design for DDR and MIPI - CPHY an CSI IPs. Owned Visa Insertion, Validation and post Silicon support for multiple IP deliveries to SoCs and couple of Test Chips.
- Contributed in UPF updates for different power architecture requirements including implementation of Power gating, Isolation & Level Shifter strategies, Cold/Warm Power Boot sequence.
- Developed and upgraded power sequence test case for validating different cold/warm boot sequence as per subsystem requirements
- Contributed in LP5 HW Training FSM Design and RTL Updates
- Managed 4 member team for VISA Design, FEBE Checks and DART Based IP RTL Delivery in a ODC set up for duration of 15 months
Senior Engineer - FPGA Design
Rockwell Automation
02.2015 - 02.2016
- Delivered FPGA Logic Design and bit file for Serial Synchronous Interface (SSI) I/O Module product as FPGA Design Engineer
- Responsible for complete FPGA RTL Design as well as functional testing
- Designed and implemented custom communication protocol interface, SSI Master Interface and Data Processing block on FPGA to establish communication between Microcontroller (UC) and Absolute Position Encoder with SSI Slave Interface.
- Driven FPGA bring up testing and contributed in product certification testing
- Developed an algorithm and Implemented FPGA Logic based wire break detection solution as per OEM Customer requirement that directly resulted in securing business order post feature demonstration
- Automated the FPGA Bit file programming with scripting to save time on fixture based programming in testing and production environment
Project Engineer
C-DAC R&D
09.2010 - 02.2015
- Worked as Project Engineer in high speed network design and network security related projects
- Studied Forward Error Correction (FEC) sub-layer and Error Correcting Codes and defined architecture of FEC block using Fire code Methodology for Proof of Concept.
- Designed Encoder and Decoder for Error Correcting Code (2112, 2080) with complex clock domain crossings for FPGA based implementation. Tested successfully with error injection and correction. Design met Bit Error Rate Testing benchmark requirements for 10G single lane and 40G Channel bonded link
- Studied different CRC algorithms for CRC computation and implemented Slicing-by-N algorithm as well as Matrix based Parallel CRC generation method for CRC32 block, compliant with Ethernet Polynomial
- Contributed in 10G Ethernet Flow Control for backpressure management in packet based network designed using VHDL for ethernet switch product and implemented same using High Level Synthesis language Bluespec System Verilog as a part of Bluespec Tool Evaluation
- Delivered specifications requirements for FPGA Power Sequencing using PWM Controller including testing scenarios for Board Power Bring-Up and built Power Monitoring scheme using Fusion Power Designer Tool for 40Gbps Interconnect prototype board
- Contributed in Intrusion Detection and Prevention System (IDPS), one of the sub-solution of Universal Threat Management Solution, consisting of a Pre-processor block, implemented on FPGA
- Designed a signature matching Logic from scratch for detecting violating threat signatures received in TCP/IP Packets. Owned Micro-architecture, RTL Design, Implementation and Functional Verification of Pre-processor block which supports over 1800 SNORT Rules and 3000 signatures
- Integration of Pre-processor block with remaining system which is implemented successfully on both Virtex-6 and Kintex-7 FPGA based boards
Education
PG Diploma - VLSI Design
Advanced Computing Training School (ACTS)
Bachelor of Engineering - Electronics and Tele-Communication
Rajarambapu Institute of Technology
Sakharale, Maharashtra 01.2005 - 01.2009
Skills
RTL Language - Verilog
Location - Current Address
Oceanus Triton, Sarjapur Road, Bellandur, Bengaluru, Karnataka, 560103
Synopsis
11, Staff Engineer (SoC Design), Qualcomm, Bengaluru, Requirement analysis, Self-Motivated, Teamwork, Communication, Interpersonal skills, Organizational skills
Skill Summary
Verilog, VHDL, System Verilog, Bluespec System Verilog, C, C++, Perl, FPGA, Digital System Design, Ethernet, FEC, SSI, DDR, MIPI, Functional Verification, Lint, CDC, UPF, Synthesis, STA, PAR, VCS, DVE, Verdi, SpyglassLP, Lintra QuestaCDC, Questasim, Xilinx's Vivado/ISE 14.4, Altera's Quartus, Fusion Power Designer
Personal Information
- Passport Number: J1690372
- Date of Birth: 10/20/87
- Gender: Male
- Nationality: Indian
- Marital Status: Married
Timeline
SoC Logic Design Engineer
Intel
07.2022 - Current
Staff Engineer (SoC Design)
Qualcomm
12.2019 - 06.2022
Chief Engineer
Samsung Research India
10.2018 - 11.2019
Senior Lead Design Engineer
Cerium Systems
02.2016 - 09.2018
Senior Engineer - FPGA Design
Rockwell Automation
02.2015 - 02.2016
Project Engineer
C-DAC R&D
09.2010 - 02.2015
Bachelor of Engineering - Electronics and Tele-Communication
Rajarambapu Institute of Technology
01.2005 - 01.2009
PG Diploma - VLSI Design
Advanced Computing Training School (ACTS)
Similar Profiles
Brenton LindseyBrenton Lindsey
Technologist - Commissioning Manager at IntelTechnologist - Commissioning Manager at Intel
Christopher CarpenterChristopher Carpenter
Automation/MFG Systems Software Engineer at IntelAutomation/MFG Systems Software Engineer at Intel
Caleb BloodworthCaleb Bloodworth
Etch Module Engineer at IntelEtch Module Engineer at Intel
Allan Zamora BolañosAllan Zamora Bolaños
Internal Audit Manager at IntelInternal Audit Manager at Intel
Madhuri KonduruMadhuri Konduru
Assistant Manager at VodafoneAssistant Manager at Vodafone