Pushpa Bakuru
Bengaluru
Summary
Organized and dependable candidate successful at managing multiple priorities with a positive attitude. Willingness to take on added responsibilities to meet team goals. Detail-oriented team player with strong organizational skills. Ability to handle multiple projects simultaneously with a high degree of accuracy.
Overview
1
1
year of professional experience
Work History
DESIGN AND VERIFICATION ENGINEER
Radiant Semiconductor Pvt Ltd
Bengaluru, India
04.2024 - Current
- Running GLS regressions and posting bugs to design team.
- Hands on experience on IP level verification environment using SV and UVM
- Good Knowledge on Code and Functional coverage analysis
- Hands on expertise with Gate Level Simulation, finds and implements corrective measures to resolve failing testcases.
- Good knowledge and hands on experience with Functional Verification including debugging regressions and Coverage closure.
Education
M.TECH - Nano-Technology
ANDHRA UNIVERSITY COLLEGE
Visakhapatnam, India09.2022
B.TECH - ECE
ANDHRA UNIVERSITY COLLEGE
Visakhapatnam, India03.2020
INTERMEDIATE - M.P.C
SRI CHAITANYA JUNIOR COLLEGE
Visakhapatnam, India04.2016
MATRICULATION -
BHASHYAM PUBLIC SCHOOL
Visakhapatnam, India04.2014
Skills
- Digital Electronics
- Verilog Programming
- Advanced Verilog & Code Coverage
- Interface
- Constraint Randomization
- Thread synchronization techniques
- Functional coverage - Cover groups, bins and cross-coverage
- System Verilog HVL
- System Verilog Assertions
- Universal Verification Methodology
- Gate-level simulations
- Code coverage analysis
- Formal verification techniques
- SoC verification
- Testbench development
- Verification planning
- Regression testing
PROJECTS
GLS (CANOPUS) - Worked at SOC level
- SOC verification covering functional and Firmware Scenarios in RTL, CPF RTL, GLS, PAGLS modes
- Debugging the Regression Failures/errors
- Peripherals understanding with AHB, APB & AXI Interface Knowledge
ROUTER 1X3 - RTL Design and Verification
Description - The Router accepts data packets on a single 8-bit port and routes them to one of the three input channels, channel_0/1/2.
Responsibilities:
- Architected the block level structure for design
- Implemented RTL using Verilog HDL
- Verified the RTL using SV
Technicalskills
Digital Electronics, Static Timing Analysis, Verilog Programming, Advanced Verilog & Code Coverage, Memories, Interface, Constraint Randomization, Thread synchronization techniques, Functional coverage - Cover groups, bins and cross-coverage, CRCDV and regression testing, System Verilog Assertions, Universal Verification Methodology
HANDS ON TRAINING
Advanced VLSI Design and Verification Course, Maven Silicon VLSI Design and Training Center, Bangalore.
Protocol knowledge
- AHB
- APB
- SPI
- UART
- I2C
Hobbies and Interests
- Cooking
- Watching movies
- Singing
- Walking
Disclaimer
I hereby declare that all the information furnished above is true to the best of my belief.
Timeline
DESIGN AND VERIFICATION ENGINEER
Radiant Semiconductor Pvt Ltd
04.2024 - Current
M.TECH - Nano-Technology
ANDHRA UNIVERSITY COLLEGE
B.TECH - ECE
ANDHRA UNIVERSITY COLLEGE
INTERMEDIATE - M.P.C
SRI CHAITANYA JUNIOR COLLEGE
MATRICULATION -
BHASHYAM PUBLIC SCHOOL