Sowmya Rachakonda

1) Verification of AMBA APB -1.0 using UVM and SV testbench architecture: APB is designed for low bandwidth control accesses, for example register interfaces on system peripherals. This bus has an address and data phase similar to AHB, but a much reduced, low complexity signal list (for example no bursts)., Verification, Developed the test bench environment and tested the APB-1.0 by using System Verilog and UVM., Generated different test cases in UVM to verify the functionality of the RTL module., Created Coverage Analysis and improved code coverage., Created Make file to run the targets., Automated the testcases to run in Regression Mode., Verilog, System Verilog, UVM, Questa sim, Vim, Gvim Editor.

2) Design and Verification of Scrambler and Descrambler and loopback using Verilog in SV : A scrambler is an algorithm that converts the input data into seemingly random output data of same length by avoiding the long sequence of same bits. A descrambler is a device that reverses the process of scrambling. It is used to recover the original data from the scrambled data. The scrambler/descrambler pair is commonly used in digital communication systems to provide data security and reduce errors., Designed an Scrambler, Descrambler Module and Developed the test bench environment and tested the Scrambler and Descrambler modules with the test cases using Verilog and SV., Verilog, SV, Vivado 

3) Verification of Synchronous FIFO using SV testbench architecture : In Synchronous FIFO, data read and write operations use the same clock frequency. Usually, they are used with high clock frequency to support high-speed systems. FIFO can store/write the wr_data at every posedge of the clock based on the wr_en signal till it is full. The write pointer gets incremented on every data write in FIFO memory. Verification of AMBA AXI -1.0 using UVM and SV testbench architecture, AXI is a new generation of AMBA bus which is intended to address the requirements of high-performance synthesizable designs. AMBA AXI is a new level of bus which sits above the AHB and APB and implements the features required for high-performance., Verification, Developed the test bench environment and tested the APB-1.0 by using System Verilog and UVM., Generated different test cases in UVM to verify the functionality of the RTL module., Created Coverage Analysis and improved code coverage., Created Make file to run the targets., Automated the testcases to run in Regression Mode., Verilog, System Verilog, UVM, Questa sim, Vim, Gvim Editor 

4) Verification of AMBA AXI -1.0 using UVM and SV testbench architecture 

 Description : 3 * AXI is a new generation of AMBA bus which is intended to address the requirements of high-performance synthesizable designs . * AMBA AXI is a new level of bus which sits above the AHB and APB and implements the features required for high-performance. * Key features of the AXI protocol include separate read and write channels, support for burst transactions, outof-order data transfers, and multiple outstanding transactions. Role : Verification Contribution : * Developed the test bench environment and tested the APB- 1.0 by using System Verilog and UVM. * Generated different test cases in UVM to verify the functionality of the RTL module. * Created Coverage Analysis and improved code coverage. * Created Make file to run the targets. * Automated the testcases to run in Regression Mode. Technology : Verilog , System Verilog , UVM . Tools : Questa sim , Vim and Gvim Editor .

5) Design and verification of UART protocol in System Verilog : UART is a Universal Asynchronous Receiver Transmitter protocol that is used for serial communication. Start bit, stop bit, and the parity bit is other overhead. Since this is asynchronous communication so here there are many things that we need to do in configuration, for instance, we should configure both devices at the same speed because the clock signal is absent., Design and Verification, Developed design and testbench in System Verilog., Also used UART ip from Vivado in developing UART tb., System Verilog in Vivado 

6) Verification of Router 1*3 using Verilog : Routing is the process of moving a packet of data from source to destination and enables messages to pass from one computer to another and eventually reach the target machine. A router is a networking device that forwards data packets between computer networks. It is connected to two or more data lines from different networks (as opposed to a network switch, which connects data lines from one single network). This project mainly emphasizes upon the study of router device, its top-level architecture, and how various sub-modules of router i.e. Register, FIFO, FSM and Synchronizer are synthesized, and simulated and finally connected to its top module. 

7) Tilt sensor to detect orientation Using Tinker cad: Tilt sensors are usually made by a cavity of some sort of cylindrical material and a conductive free mass inside. In this project, the sensor consists of a conductive plate. When the sensor gets power, the rolling ball falls to the bottom of the sensor to form an electrical connection. This orientation sensor is used in applications such as Video cameras, Robotic technology, Aircraft controls, etc. 

8) Performance of sequential circuits using various D - flip flops: Design of various up and down counters related to VLSI integrated circuits for low power applications using the TANNER EDA tool.

Date of Birth: 09/25/2000

Gender: Female