Radhika R
SOC Design Engineer
Palakkad
Summary
Accomplished SOC RTL Design and Integration Engineer at Intel, with over 5 years of experience, including impactful contributions to Xeon Server projects. Excelled in automation framework development in Python, showcasing strong programming and collaborative skills. Proven track record in enhancing design efficiency and cross-functional team leadership. Formerly engaged with Interface IP design and integration.
Overview
5
5
years of professional experience
6
6
years of post-secondary education
Work History
SOC RTL Design and Integration
Intel
Bengaluru
2019.07 - Current
- Worked as an RTL Integrator/Designer in Xeon Server projects in the following domains:
o Clock fabric integration: Developed an automation framework in python to integrate clock fabric into the SOC, generate SD and validation collaterals for the integrated clock fabric
o Interface IP Design: Helped develop an Interface IP to connect the top die and bottom die for a 3D stacked Xeon server design with the dies on different process node (intel 3 and intel 18A). Also developed an automation framework to integrate the IP into the SOC as per the changing specifications. The flow also dumped out collaterals which can be used as reference by downstream consumers like verification and SD
o Strap Decoder Implementation: Helped develop an automation flow for strap decoder implementation in SOC and integrated the same into the model
o Thermal Fabric Implementation for Xeon Servers
o Managed the GIT repository for multiple Xeon Server Projects: Handled tasks like monitoring the GIT repository, making sure only necessary changes are being pushed into the repo by users, resolving issues popping up in GIT repo and so on
o DFT RTL integration into the SOC: Have started working on TAP, BSCAN implementation for SOCs
• Developed experience in performing RTL quality checks like Spyglass LINT, Spyglass CDC and basic understanding of UPF
• Worked efficiently across cross functional teams and collaborated with the verification team in debugging and resolving design issues.
Education
MTECH - MicroElectronics And VLSI Design
IIT Madras
Chennai 2017.06 - 2019.06
BTECH - Electronics And Communications Engineering
NSS College of Engineering
Palakkad 2012.06 - 2016.06
Skills
● Programming Languages : C++, Python,Perl
● HDLs : Verilog, System Verilog
● Tools : SGLINT, SGCDC, Synopsis Verdi, UPF, MATLAB
● GIT
Additional Information
CO-CURRICULAR ACTIVITIES
● Attended Embedded computing workshop on Arduino basics conducted by EDC cell, NSSCE in Jan 2014
● Attended Robo Vision –A 2 day workshop Conducted by Technophilia Systems in Association with Robotics and Computer Applications institute of USA in Sept 2013.
● IEEE National Conference on Communication ,Signal Processing and Networking conducted by NSS College of Engineering in October 2014
● Participated and secured first prize in ‘Desafiador’ competition conducted as a part of Tech fest ‘Gamaya ‘at NSS College of Engineering in Sept 2014.
Timeline
SOC RTL Design and Integration
Intel
2019.07 - Current
MTECH - MicroElectronics And VLSI Design
IIT Madras
2017.06 - 2019.06
BTECH - Electronics And Communications Engineering
NSS College of Engineering
2012.06 - 2016.06
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