Raghu Sanapathi
Bengaluru
Summary
Results-driven Physical Design Engineer with 7+ years of experience at AMD, specializing in high-performance chip design, implementation, and optimization. Proven expertise in managing complex physical design flows, leveraging EDA tools, and driving innovative solutions for cutting-edge semiconductor projects. Seeking to contribute my deep technical knowledge and leadership skills to a dynamic team, ensuring the successful delivery of high-quality, scalable designs in fast-paced environments.
Overview
7
7
years of professional experience
Work History
Senior Silicon Design Engineer
AMD
08.2021 - Current
- Fullchip design experience in designing L3 cache IP and ccx (core complex is core+L3) of x86 CPU Architecture(5+ tape-out completed).
- Floorplanning of blocks/tiles created and placing the interface pins of all the blocks
- Buffer fabric pushdown (creating inv/buf repeater structures for high freq data signals to help achieve the block level timing)
- PNR exposure with 0.5m inst count clocking above 4 Ghz.
- Formality and block level timing experience.
Junior Consultant Engineer
Capgemini Engineering
11.2017 - 07.2021
- Block level implementation (RTL2GDSII) using Synopsys tools.
- Worked on Intel server projects using intel RDT flow with in house foundry's tech nodes ranging from 7nm to 10nm
- Experience in working in analog and digital partitions clocking at 2.8 - 3Ghz
- Built manual clock tree for analog partition in eco phase to counter hold issues.
- Expertise in clock tree synthesis (CTS), timing closure, LEC and other block level signoff checks including EMIR, Caliber orientated DRC's.
Education
Bachelors of Engineering (BE) - Electronics and Telecommunication
Maharashtra Institute of Technology
05.2017
Higher Secondary Education - Computer Science and mathematics
Kendriya Vidyalaya B.E.G
03.2013
Skills
- Fullchip Design
- Place and Route (PNR)
- Latency optimisation
- Timing closure
- Synthesis
- Floorplanning
- TCL - Proficient
- Perl - Amateur
- Python - Beginner
Personal Information
Title: Senior Silicon Design Engineer
Timeline
Senior Silicon Design Engineer
AMD
08.2021 - Current
Junior Consultant Engineer
Capgemini Engineering
11.2017 - 07.2021
Bachelors of Engineering (BE) - Electronics and Telecommunication
Maharashtra Institute of Technology
Higher Secondary Education - Computer Science and mathematics
Kendriya Vidyalaya B.E.G
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