Rahul Jakhodia
Physical Design Engineer
Bangalore
Summary
- Accomplished Physical Design Engineer proficient at Netlist to GDS implementation, STA, IR/EM, and PV
- Currently contributing expertise as a Graphics Hardware Engineer at Intel India Pvt Ltd.
- Strong fundamentals in Physical Design execution through the handling of various blocks in multiple projects with freq >1.7GHz and 4M gate count
- Extensive experience in Floor Planning, Placement, CTS, Routing optimization and TCL/Shell scripting
- Worked on technology nodes from 28nm to 3nm
Overview
7
7
years of professional experience
4
4
years of post-secondary education
Work History
GPU Physical Design Engineer
Intel
5 2022 - Current
- Discrete GPU, TSMC N5P
- Leading floorplanning for an IP, achieving high-quality floorplans with metrics such as utilization, inter-partition routability, macro placement, and global cell placement.
- Achieved 80% macro placement stability and 75% pin placement stability during the earlier design stages, enabling faster stabilization of Place and Route (PnR) recipes.
- Managed multiple partitions for PnR implementation, optimizing RP placement and unit bounding to control congestion and maintain timing integrity.
- Discrete GPU, TSMC N5
- Orchestrated implementation of two partitions within section, realizing RTL to GDS with Gate Count of 4.5M and 3M, operating at 3.5GHz and 1.75GHz
- Attained milestones across implementation cycle, fostering seamless collaboration with cross-functional teams to resolve challenges
- Demonstrated strong grasp of placement strategies, addressing over 1000 Relative Placements (RPs) within RP-dominant partition
- Effectively managed timing by optimizing logic depth, rectifying inter-timing violations, and creating appropriate bounds for unit instances
- Expertly resolved congestion issues, enhancing routing efficiency through strategic RP adjustments and placement blockages
- Discrete GPU, TSMC N5
- Led ECO implementation of eight partitions across sections
- Verified functional ECO feasibility and executed it in 4 partitions, ensuring comprehensive timing and calibre violation closure
- Successfully handled partitions with dependencies on full chip, delivering results within stringent deadlines
- Achieved high quality results through efficient task execution and adherence to re-use partition guidelines
- Integrated GPU, TSMC N5
- Contributed to implementation of 3 partitions in Section, effectively executing RTL to Post-CTS implementation
- Ensured compliance with given RTL and partition size guidelines, achieving efficient SIP execution.
Physical Design Engineer, II
Synopsys
10.2019 - 05.2022
- Projects
- PPA optimization of processor core and Netlist to GDS implementation
- Enhanced implementation flow, achieving 8% area improvement by densely packing various Vt devices
- Strengthened power coverage using optimized PG planning, contributing to improved implementation quality
- Devised strategies to address timing constraints, resulting in 8% improvement in timing margin through cell bounding, magnet placement, and path grouping methods
- Signoff Methodology
- Developed TCL script to identify cells under DRC markers reported by ICV, enhancing tool compatibility across ICC2 and ICV
- Created streamlined push-button signoff methodology based on RM-flow for latest process technology node
- Cell timing optimization
- Navigated complex timing challenges faced by processor core implementation, bridging gap between power, area, and timing requirements
- Strategically leveraged "Multiple Don't Use" trials and library's variant-aware cells to masterfully mitigate timing violations, achieve stringent timing targets
- Cell Routability Enhancement
- Conducted comprehensive analyses of ability of library cells to be routed across multiple releases and advanced process technology nodes
- Spearheaded efforts to standardize physical verification flows for consistency across multiple projects and teams
Physical Design Engineer
Insilico
08.2017 - 10.2019
- Projects
- Cisco, Networking Group, Switch SoC
- Successfully completed physical design (Netlist to GDS) of 800K+ gate digital macro in SS14nm, mitigating congestion and timing issues with Calibre
- Cisco, Networking Group, Switch SoC
- Successfully completed physical design (Netlist to GDS) of 270k-cell macro in 28nm, achieving timing/PV closure with advanced QoR techniques and DRC fixes.
Education
Bachelor of Engineering - Electronics and Communication
B K Birla Institute of Engineering & Technology
Pilani, Rajasthan 01.2013 - 04.2017
Skills
Knowledge on full PNR execution cycle including signoff flows
Hands on with EDA tools (ICC2, Fusion Compiler, PT, DC, Calibre)
Experince of Low Power Methodologies
Accomplishments
- ICCII – ICC2 Jump Start Training
- FC – Fusion Compiler: Design Implementation
- VLSI Certificate Course at Incise Infotech Pvt Ltd
- Verilog, RTL to netlist flow, Netlist to GDS implementation, and TCL scripting
Timeline
Physical Design Engineer, II
Synopsys
10.2019 - 05.2022
Physical Design Engineer
Insilico
08.2017 - 10.2019
Bachelor of Engineering - Electronics and Communication
B K Birla Institute of Engineering & Technology
01.2013 - 04.2017
GPU Physical Design Engineer
Intel
5 2022 - Current
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