RAHUL KASHYAP
Design Verification Engineer
Bengaluru
Summary
Experienced design verification professional with a proven track record in CPU and NoC verification. Successfully developed robust verification environments, implementing advanced methodologies that led to significant coverage improvements and high-quality results. Adept at problem-solving and critical thinking, consistently delivering projects on time and exceeding expectations.
Overview
3
3
years of professional experience
Work History
Design Verification(NoC)
Baya Systems
08.2023 - Current
- Developed robust AXI 5 lite Protocol checker using SystemVerilog Assertions, seamlessly integrated with CSR Controller, and successfully verified its functionality.
- Demonstrated expertise in verifying Performance Monitor designs by creating Directed and Randomized Sequences, applying constraints as per Testplan using UVM RAL, and consistently meeting project deadlines.
- Achieved significant coverage improvements by meticulously writing Functional and Parameter coverage using Coverpoints, aligning with designer expectations, and enhancing overall verification quality.
- Spearheaded verification of Multicluster (Chiplets) designs by developing directed configurations in Python, meticulously debugging through TX/RX XTOR, and efficiently resolving HW simulation failures using log and waveform analysis.
- Engineered Egress and Ingress checkers for boundary bridges across all clusters, ensuring packet format alignment and preventing misalignments within clusters.
- Successfully designed and executed Back-to-Back, Read followed by Write Sequences for RO, RW, WO for bandwidth testing via AXI5-lite and AXI4 VIP Protocols.
Design Verification(CPU)
Qualcomm
07.2021 - 02.2023
CPUSS CSR Verification with AHB Protocol
- Spearheaded verification of CPU Subsystem (CPUSS) with AHB Protocol, crafting directed sequences aligned with Testplan, applying randomized constraints using UVM RAL, and expertly debugging failures using advanced log and waveform analysis. Possess deep knowledge of CPUSS design and Cache Coherency.
Integrated APB Verification IPs within CPUSS TB
- Successfully integrated ARM IP core or VIP with CPUSS peripherals, facilitating seamless interaction in round-robin method. Mapped VIP signals with design, managed UVM_config_db Master/Slave settings, and orchestrated transaction flow to validate peripherals' registers mapping..
Verification Plan for Fusa Fault Aggregator
- Developed Verification Plan for Fusa Fault Aggregator (DUT), ensuring adherence to Quality State Q3 specifications. Crafted directed test cases, clock and reset-based tests, and interrupts tests, ensuring thorough coverage of CSR Register functionalities.
Functional Coverage
- Enhanced Functional Coverage for Fusa Fault Aggregator, meticulously designing coverage bins to boost coverage metrics. Collaborated closely with team to add test cases aligned with functionality, ensuring comprehensive coverage.
Education
MTech in Electronics and Communication with Majors in Microelectronics -
Indian Institute of Information Technology Allahabad
08.2021
BTech In Electronics & Communication -
Gurunanak Institute of Technology
Kolkata, India08.2017
Skills
Language - UVM, System Verilog, Verilog, C, TCL Makefile, Git, Python, Jinja Template
undefinedAccomplishments
- Received Award within CPU Team as "QCT india CPU Team" for continuous effort and dedication from Senior Director, Qualcomm 2023.
- Received Certification in "Introduction to FPGA Design For Embedded Systems" from University of Colorado
Projects
Hardware Trojan Detection Framework in Hardware Security (MTech Thesis Project)
- Hardware Trojan Detection Framework in 3rd Party digital IPs of 128bit AES Chip level Trojan by analyzing ASIC DFT Insertion on AES Benchmark, Power Vector Analysis on AES Benchmarks to detect the Hardware Trojan. Gained Expertise in Verilog, Xilinx Vivado, Verdi, Synopsys VSC, Formality tool (LEC)
Design & Implementation 32 RISC Processor using Verilog (MTech Projects)
- Implemented 32-bit 5 Stage RISC V Architecture-based processor with and without pipeline Architecture to perform ALU operations, Also handled and tackled data Hazards, Structural hazards and also control hazards by applying various methodologies of stalling (NOP). Gained Expertise in Intel Quartus II, Xilinx Vivado, FPGA Board, and Verilog, RISC V.
Design Fully Synthesized Asynchronous FIFO For Clock Domain Crossing using Verilog (MTech Projects)
- Design must take into account issues such as data latency, data synchronization, and data integrity to ensure that the FIFO operates reliably and efficiently. The design includes logic to synchronize the data between the two domains to ensure that data is not lost or corrupted during the transfer.
Timeline
Design Verification(NoC)
Baya Systems
08.2023 - Current
Design Verification(CPU)
Qualcomm
07.2021 - 02.2023
MTech in Electronics and Communication with Majors in Microelectronics -
Indian Institute of Information Technology Allahabad
BTech In Electronics & Communication -
Gurunanak Institute of Technology
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