Summary
Overview
Work History
Education
Skills
Certification
Accomplishments
Projects
Extracurricular Activities
Timeline
Generic

Rahul Lodwal

Delhi

Summary

Design Verification Engineer with 3 years of experience in digital front-end verification, EDA tool enablement, and automation. Proficient in SystemVerilog, UVM, and industry-standard verification tools. Skilled in debugging, coverage-driven verification, optimizing workflows, and scripting. Experienced in collaborating with cross-functional teams and EDA vendors to enhance methodologies. Recognized for innovation in AMS-DFT verification, with a published paper at the European Test Symposium 2024. Currently mentoring an intern in Functional Verification domain.

Overview

3
3
years of professional experience
1
1
Certification

Work History

Senior Digital Design Engineer

NXP Semiconductors
07.2022 - Current
  • As a Verification Engineer, I debug UVM-based testbenches for functional verification.
  • I specialize in coverage-driven verification using SystemVerilog, and constraint random techniques.
  • Proficient in Xcelium, vManager, I ensure efficient verification workflows.
  • Having exposure, of protocols like AXI,Ethernet, I2C, APB, I aim to enhance verification methodologies to improve efficiency.
  • The role also includes delivering sanity-clean testbenches in Xcelium for various projects to assist the AMS team, as well as collaborating with EDA vendors to resolve critical issues and enhance verification methodologies.
  • Spearheaded an AMS-DFT Innovation activity, re-used the functional verification environment to generate and run AMS DFT testcases in System Verilog as well as UVM environment.
  • Developed a Python-based automation framework to process Procedural Description Language (PDL) files for AMS verification and convert it into UVM based testcase.
  • Published a research paper in AMS DFT Innovation activity in European Test Symposium(ETS) which was held in Hague, Netherlands.

Education

B.E. - Electronics & Comm.

Netaji Subhas University of Technology
01.2022

Skills

  • Functional verification
  • LSF
  • VManager
  • Xcelium
  • Simvision
  • System Verilog
  • UVM
  • Verilog
  • Python
  • AXI
  • Ethernet
  • I2C
  • JTAG
  • APB

Certification

Successfully completed badge exam of System Verilog for Design and Verification by Cadence.

Successfully completed badge exam of UVM for Design and Verification by Cadence.

Accomplishments

  • Won SPOT Award with NXP for delivering sanity clean TB using Xcelium.
  • Innovation Award with NXP for presenting research paper in ETS conference.
  • Cheers for Peers Award for enabling AMS DFT flow for a Business Line project.
  • Active Member of music club at NXP.

Projects

I2C Verification in Ranger5 Project (NXP), Developed and executed random testcases for error handling scenarios., Implemented functional coverage models to track protocol compliance., Debugged failures using waveform analysis., Collaborated with RTL designers to resolve design issues. 

AXI4 UVM Environment Development (Project Orion), Built a simplified, modular UVM testbench for verifying AXI4 protocol behavior., Focused on validating core protocol features., Developed sequences to verify INCR and FIXED bursts., Implemented functional coverage for key AXI signals., Used Simvision for waveform debugging. AMS-DFT Innovation Activity (NXP), Automated UVM-based AMS DFT test case generation using Python., Executed JTAG FSM using python script., Reduced manual test development time. LSF Memory Optimization Flow for vManager (NXP), Designed a Python script optimizing Load Sharing Facility memory allocation., Generated optimized VSIF files., Improved memory efficiency by 90%.

Extracurricular Activities

Won SPOT Award with NXP for delivering sanity clean TB using Xcelium. Innovation Award with NXP for presenting research paper in ETS conference. Cheers for Peers Award for enabling AMS DFT flow for a Business Line project. Active Member of music club at NXP.

Timeline

Senior Digital Design Engineer

NXP Semiconductors
07.2022 - Current

B.E. - Electronics & Comm.

Netaji Subhas University of Technology

Similar Profiles

CREATE PROFILE
Rahul Lodwal