Summary
Overview
Work History
Education
Skills
Accomplishments
Personal Information
Timeline
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Rahul Purohit

Hyderabad,TG

Summary

Experienced Senior Verification Engineer with 17 years of diverse experience in driving the verification of complex SoCs, CPU cores, and cutting-edge microarchitectures. Proven ability to scale teams, innovate test strategies, and deliver successful verification outcomes within tight schedules. Recognized for strong leadership skills, proactive problem-solving approach, and excellent collaboration with cross-functional and multi-site teams.

Overview

17
17
years of professional experience

Work History

Senior Verification Lead

AMD Inc.
08.2011 - Current
  • Technical Leadership: Spearheaded verification initiatives for critical CPU cores (X86 Jaguar and Zen Family) and SoC components, setting testbench architecture, regression strategies, and coverage goals
  • Team Management & Mentorship: Built and led high-performance teams responsible for verification strategy, advanced debugging, and coverage closure
  • Guided junior to mid-level engineers, enabling quick ramp-up and consistent execution
  • Cross-Site Collaboration: Coordinated complex feature implementations and verification strategies across multiple global locations
  • Emphasized robust communication to ensure stakeholder alignment and timely deliveries
  • Innovation & Process Improvement: Actively participated in CPU verification committees and coverage working groups, standardizing and improving methodologies
  • Streamlined coverage processes, test planning, and infrastructure scaling
  • Key Accomplishments: Achieved top ratings for major product releases by ensuring on-schedule verification closure with minimal bugs in production
  • Raised external visibility through presentations, influencing broader verification best practices across AMD
  • Mentored new hires in cross-functional domains, fostering a culture of learning and cross-pollination of ideas
  • Identified critical bugs through thorough regression testing, ensuring product reliability.
  • Established strong working relationships with design engineers for efficient knowledge transfer and collaboration throughout the verification process.
  • Contributed to continuous improvement initiatives by providing feedback on existing processes and suggesting enhancements.
  • Collaborated with cross-functional teams to ensure seamless integration of components, resulting in a robust final product.
  • Mentored junior engineers, fostering a collaborative work environment and improving skill sets.
  • Developed comprehensive test cases to validate design specifications, increasing overall product quality.
  • Implemented coverage-driven verification techniques for improved test effectiveness and resource allocation.

Front-End Verification Engineer

Cypress Semiconductors
01.2008 - 01.2011
  • SoC-Level Verification: Worked on AHB-based SoCs utilizing ARM CM0 and 8051 cores, focusing on both constrained-random and directed verification
  • Key Contributions: Led verification tasks for bus interconnects (AHB Bridge), IP blocks (Decimator, DMA controller, Interrupt controller), and CPU-memory subsystems
  • Performed gate-level simulation and IR drop analysis to validate robust SoC performance
  • Created test strategies for PSoC3 modules (PHUB, Decimator), ensuring coverage and timely sign-off
  • Team Collaboration & Tool Mastery: Leveraged Verilog, SystemVerilog, and Vera-based testbenches
  • Wrote scripts (Perl, Shell) to automate repetitive tasks, improving productivity
  • Accomplishments & Recognition: Contributed to Cypress's 'Design Productivity Initiative,' driving methodology enhancements and process efficiencies

Education

M.Tech - VLSI & Embedded Systems

IIIT-Hyderabad
01.2008

B.E. - Electronics Engineering

SRTMU Nanded
01.2005

Skills

  • CPU Verification Expertise
  • Technical Project Oversight
  • Collaborative Team Development
  • Operational Efficiency Improvement
  • Constrained Testing Methodology
  • Directed Testing
  • Coverage Assessment
  • Calm under pressure
  • Verilog Design Expertise
  • Proficient in SystemVerilog
  • Experience with OVM/UVM Methodologies
  • Experience with AHB Protocol
  • Debugging Native Low Power Simulations
  • Gate-Level Testing
  • Scripting (Perl, Shell)
  • Tools (VCS, ModelSim)
  • Effective Problem-Solving Techniques
  • Effective Team Collaboration
  • Supportive Mindset

Accomplishments

  • Gate Scholarship from the Ministry of Human Resources and Development; qualified for National Mathematics Olympiad.
  • Consistent track record of on-time, high-quality releases. Multiple accolades from management recognizing leadership and innovative approaches to verification.
  • Known for ability to ramp up new technologies quickly and impart knowledge effectively to teams, elevating overall project execution.

Personal Information

Title: Senior Verification Engineer

Timeline

Senior Verification Lead

AMD Inc.
08.2011 - Current

Front-End Verification Engineer

Cypress Semiconductors
01.2008 - 01.2011

B.E. - Electronics Engineering

SRTMU Nanded

M.Tech - VLSI & Embedded Systems

IIIT-Hyderabad

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Rahul Purohit