Rahul Sharma

Dynamic Analog Design Engineer with experience at Lemon Flip Solutions, specializing in integrated circuit design and mixed-signal applications. Proficient in Cadence Virtuoso and skilled in layout verification, I have successfully optimized circuit performance and enhanced designs in advanced technology nodes. A problem-solver with strong analytical abilities, I excel in delivering innovative solutions.

• Analog Electronics
• Design
• CMOS Design
• Low Power Analysis
• Advance Digital System Design
• VLSI System Design
• FPGA Design
• Advanced Computer Architecture
• Verification Engineer

• Qualified GATE 2020, 2021, 2022
• Udemy online courses Physical design, system Verilog
• Cadence course: Virtuoso schematic editor, Virtuoso Layout Design Basic, Virtuoso Layout Pro, Virtuoso Layout XL, SKILL Language, Virtuoso Layout Advance Node, verification side.

Advanced Low-Power SRAM Design Techniques at 16nm Node: Combining Multi-Threshold Voltage, MOSFET Stacking, and Body Biasing, IEEE (15th ICCCNT), IIT Mandi

• Analog IC Design
• ASIC Design
• Low Power Design
• Physical Design
• CMOS Design
• Physical Verification

• Advanced Low-Power SRAM Design Techniques at 16nm Node: Combining Techniques ( Aug’2023-May’2024)

Guide: Assistant. Prof. Dr. Prakash Kodali, NIT Warangal

– Tools & technologies used: Cadence Virtuoso,16nm Technology node – Analysis of my results were done comparing with published data like power analysis and SNM. – Using 16nm technology node for making SRAM cell. – 10 T Proposed SRAM cell using body biasing and multi-threshold Mosfet and stacking. – Analysis the static and dynamic power of proposed SRAM cell and improve the power dissipations compare to    reference paper.

• Developed an Advanced Traffic light controller using FPGA Artix-7 (Dec’2023)

Guide: Prof. Dr. T . Kishore Kumar, NIT Warangal

– Tools & technologies used: Vivado and FPGA Board – Develop Verilog code of advanced traffic light controller. – Dump the code in FPGA Artix-7. – Analysis of the signal, power, LUT, and slice used in FPGA.

• Power Reduction by using clock gating technique (march'2023)

Guide: Assistant Prof. Dr. Prithvi Pothupogu, NIT Warangal

– Tools & technologies used: Vivado Tool – Develop Verilog code of sequential circuit (Register, Ram, Rom) and clock gating. – Analysis of the power both static and dynamic. – Static power is almost constant but dynamic power varies while changing clock frequencies

• Seminar on “RIBBON FET” Intel upcoming project (Dec’2023)

Guide: Assistant Prof. Dr. Prithvi Pothupogu, NIT Warangal

– Ribbon FET is an upcoming new technology after the saturation of FinFET. – Ribbon FETs offer highly flexible channels that accommodate more power-intensive applications.. – In this also talk about Power Via.

• Teaching Assistant (TA), worked as a TA in the Digital System Lab
• Teaching Assistant (TA) , Worked as TA in Basic Analog Electronic Lab