Summary
Overview
Work History
Education
Skills
Languages
Certification
Accomplishments
Timeline
Generic
Rajat Sugandhi

Rajat Sugandhi

Bengaluru

Summary

Lead Validation Engineer at Texas Instruments, I previously held roles as Analog Design Engineer at Samsung Semiconductor India Research and as Analog Engineer at Texas Instruments. My experience spans RF data converters, high-speed interfaces, and FinFET technologies. I am interested in pursuing deeper study at the intersection of VLSI design and semiconductor physics through research in VLSI, photonics, and quantum engineering.

Overview

7
7
years of professional experience
5
5
Certifications

Work History

Lead Analog Validation Engineer

Texas Instruments
Bangalore
01.2026 - Current
  • Responsible for full chip validation of MIPI D-PHY interfaces for FPD devices. Work includes developing validation plans, executing silicon bring-up, and verifying high-speed data paths across PVT conditions. Involved in debugging link-level issues such as timing margins, jitter, lane synchronization, and signal integrity. Work also includes the correlation between simulation and silicon measurements.

ASSOCIATE DESIGN ENGINEER

Samsung Semiconductor India Research (SSIR)
Bangalore
06.2024 - 01.2026
  • LEADING ANALOG CIRCUIT DESIGN AND VERIFICATION FOR DC-PHY SUBSYSTEMS IN ADVANCED NODES (3NM TO 2NM).
  • DESIGNED AND VALIDATED KEY BLOCKS INCLUDING LPRX, LPCD, AND CLOCK MULTIPLIERS.
  • SUCCESSFULLY DELIVERED DESIGNS FOR TWO TESTCHIPS AND ONE MASS PRODUCTION DEVICE, MEETING AGGRESSIVE PPA AND TAPEOUT TIMELINES.
  • RESPONSIBLE FOR SCHEMATIC DESIGN, SIMULATION, LAYOUT REVIEW, AND POST-LAYOUT VERIFICATION ACROSS MULTIPLE PVT CORNERS.

ANALOG ENGINEER

Texas Instruments
Bangalore
07.2019 - 05.2024
  • ANALOG DESIGN(DEC 2022 – JUNE 2024 - 1.5YEARS

Design for high-speed Retimer-based Time Domain Analog to Digital Converter. AMS Simulating for Voltage to Delay Converter.

  • PRE-SILICON VALIDATION(AUG 2021 – DEC 2022 - 1 YEAR)

Modelling of High-speed Time Domain ADC to generate Power-up and Background Calibration method with MATLAB. Implementing the same in Firmware. AMS Verification of high-speed Retimer by generating Verilog model and Firmware.

  • POST SILICON VALIDATION(JUL 2019 – JUL 2021 - 2 YEARS)

Post Silicon Validation for AFE80xx, including IP verification and generating a trim algorithm, and validating the functionality of new architectural features. Responsible for the development of methodologies, execution of validation plans/ coverage, and triage of failures for Stability and Concurrency Validation for AFE80xx, a high-performance, wide bandwidth multi-channel transceiver with 8T8R. Including EVM Design for higher frequency with High Bandwidth Matching Design.

Intern

Texas Instruments
Bangalore
01.2019 - 06.2019
  • Developing high power Nanosecond Pulse Laser Driver using a GaN FET to study properties of CdZnTe pixel detectors.

Understood photon interactions with semiconductor detectors and built an experimental setup combining optics and electronics to generate controlled light pulses.

Education

Bachelor of Engineering - Electronics And Communication Engineering

Dayananda Sagar College of Engineering
Bangalore
05-2019

Skills

  • VHDL
  • Verilog
  • RF Matching
  • Ansys HFSS
  • OrCAD
  • LabVIEW
  • Simulink
  • MATLAB
  • Xilinx
  • Vivado
  • Modelsim
  • SimVision
  • cadence,
  • Python
  • Arduino IDE
  • Synopsys custom compiler

Languages

English
Advanced (C1)
C1
Hindi
Native
Native

Certification

“Workshop on IOT & Embedded System Design” by Texas Instruments

Accomplishments

Employee of Month at SSIR (Nov 2024)

Timeline

Lead Analog Validation Engineer

Texas Instruments
01.2026 - Current

ASSOCIATE DESIGN ENGINEER

Samsung Semiconductor India Research (SSIR)
06.2024 - 01.2026

ANALOG ENGINEER

Texas Instruments
07.2019 - 05.2024

Intern

Texas Instruments
01.2019 - 06.2019

Bachelor of Engineering - Electronics And Communication Engineering

Dayananda Sagar College of Engineering
Rajat Sugandhi