Rajeev Kumar
Hyderabad
Summary
A highly motivated employee with a desire to take on challenging problems. Have good problem-solving and analytical skills.
Overview
2
2
years of professional experience
Work History
PPE RISCV DEV TEST INFRA (Without RTL Support)
Rajeev
Hyderabad
03.2024 - Current
- PPE code can be tested without RTL support
- Improved time consuming for running a test cases by 83%, with RTL support it used to take 80 to 90 minutes but with this new dev test infra it's taking 15 minutes.
- Dependency on Hardware is minimized.
- Previously there were no debugger, now it's easy to debug the code with the help of gdb debugger.
- Improved code maintenance by integrating our PPE code with Pipeline to have nightly build.
Porting PPE Assembly Code to RISCV C Code
Rajeev
Hyderabad
05.2023 - 03.2024
- Ported 11b/g/n features to RISC-V C code.
- Ported 11ax features, including the sounding mechanisms.
- Optimized the critical time taken by PPE to trigger the H/w by 43% .
Mapping PPE Assembly to PPE RISCV Assembly
Rajeev
Hyderabad
08.2022 - 04.2023
- One-to-many mapping of proprietary assembly to RISC-V assembly instructions for most of the ISA.
- I added PUSH and POP instructions, which are not a basic RISC-V ISA.
Education
M.Tech - Computer Science And Engineering (8.74/10)
BITS PILANI HYDERABAD
Hyderabad07-2022
B.Tech - Computer Science And Engineering (7.96/10)
Yeshwantrao Chavan College of Engineering
Nagpur, Maharashtra07-2019
Skills
- Assembly Coding
- RISC-V ISA
- IEEE 80211 ( 11n/g/n/ax)
- Python Automation
- GDB debugger
- Computer Architectire
- Operating System
- Computer Networking
Timeline
PPE RISCV DEV TEST INFRA (Without RTL Support)
Rajeev
03.2024 - Current
Porting PPE Assembly Code to RISCV C Code
Rajeev
05.2023 - 03.2024
Mapping PPE Assembly to PPE RISCV Assembly
Rajeev
08.2022 - 04.2023
M.Tech - Computer Science And Engineering (8.74/10)
BITS PILANI HYDERABAD
B.Tech - Computer Science And Engineering (7.96/10)
Yeshwantrao Chavan College of Engineering
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