Summary
Overview
Work History
Education
Skills
Websites
Academic Publications
Timeline
Generic

Rajendra Prasad Nayak

Bangalore

Summary

Detail-oriented team player with strong organizational skills. Effective at managing and prioritizing multiple projects simultaneously while maintaining a high degree of accuracy.

Overview

8
8
years of professional experience

Work History

Senior Engineer, DDR PHY Bench Characterization Team

Qualcomm
04.2018 - Current
  • Characterization of DDR PHY Internal IP circuitry using bench instruments like oscilloscope, pattern generator, motherboard
  • Assist cross functional teams in identifying and debug DDR issues seen in system
  • Ensuring JEDEC compliance for meeting specs related to power and timing
  • Analyzing large set of bench and ATE data to give feedback to design team for circuit improvisation
  • Solving and providing technical support for customer related issues(SLT & RMA) related to DDR and maintaining DPPM within limit.

Senior Product Engineer

Sandisk (Western Digital)
01.2017 - 03.2018
  • Development of test solutions for USB NAND flash memory
  • Collaboration with systems and reliability teams to meet the timely delivery of product with ensuring quality
  • Leading the manufacturing factory and analyze the failures and understand issues related to testers
  • Gathering huge set of manufacturing yield data from factory team and analyze them for improvement of yield by fine-tuning the test suite
  • Perform debug and root cause for SLTs and RMAs.

Education

MTech / VLSI and Embedded Systems Engg. -

Indraprastha Institute of Information Technology (IIIT) DELHI
03.2017

Skills

  • Good knowledge of DDR PHY circuitry, LPDDR4/4X, LPDDR5/5X
  • Good in Memory Validation
  • Good experience in Silicon debug
  • Experience in use of Oscilloscope, Pattern generator, TCU, Motherboard
  • Familiar with JTAG Protocol and Lauterbach Trace32
  • Strong analytical and problem solving skills
  • Good Understanding in Digital Logic Design
  • Programming knowledge and experience in C, C, python
  • HDL knowledge in Verilog
  • Basic Knowledge of Full Chip design flow process from RTL Design to GDS flow
  • Basic Knowledge of AMBA, SPI protocol

Academic Publications

Low power ring oscillator for IoT applications, Analog Integrated Circuits and Signal Processing, 93, 2, 2017, 257-263, https://link.springer.com/article/10.1007/s10470-017-1015-2

Timeline

Senior Engineer, DDR PHY Bench Characterization Team

Qualcomm
04.2018 - Current

Senior Product Engineer

Sandisk (Western Digital)
01.2017 - 03.2018

MTech / VLSI and Embedded Systems Engg. -

Indraprastha Institute of Information Technology (IIIT) DELHI

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