Rajesh C. Junghare

Innovative Package Development Product Engineer at Micron Technology with expertise in semiconductor physics and root cause analysis. Emerging leader with proven record in enhancing yield through AI-driven data analysis and mentoring junior engineers. Adept at managing product lifecycles and collaborating across teams to tackle manufacturing challenges effectively.

Date of Birth

31th March 1991

Address

Belekar Lay Out, Ward No.-11, Kalmeshwar,

Dist-Nagpur-441501, 

Maharashtra, India

Hobbies

Listening Music,

Travelling by Bike to nearby places,

Gardening, Farming

• Attended a short course on 'Modelling and Simulation of Nano-Transistors' held by IIT Kanpur
• Attended the INUP hands-on training workshop on nanofabrication technologies held at IIT Bombay from January 18 to 22, 2016
• Attended a workshop held by SM Solutions on RF systems and design challenges

Title: Modelling and simulation of 2D Semiconductor based field effect transistors by ab-initio tight binding based NEGF method

Tools Used: Quantum ESPRESSO, Wannier 90, NanoTCAD ViDES, C language and Python.

Title: Design and Fabrication of MEMS based UNCD (UltraNanoCrystalineDiamonds) Disk Resonator for RF application Tools Used: COMSOL MultiPhysics, CoventorWare, MATLAB

Title: A novel 4-bit arithmetic logic unit design for power and area optimization

Tools Used: Tanner EDA

Title: Micro Cantilever Sensing Platform for Agriculture Application

Tools Used: Fabrication Tool, Laser Engraving System etc.

Title: Design of LNA at 2.47 GHz for Wireless LAN application

Tools Used: Agilent ADS,

• Student editor of newsletter “Drishti” of Center for VLSI and Nanotechnology, VNIT Nagpur.
• Mentored the group of students to build ground penetrating radar (GPR) at ROCEM which participated in Google Lunar X Prize competition organized by Team Indus.
• Experience of 6 months in Internship at SM solutions in area of RF IC design.
• Acted as College Representative of J D College of Engineering during B. E. to Rashtrasant Tukadoji Maharaj Nagpur University.
• Acted as Treasurer for IEEE Student Forum and Organiser in various events held at College Level.
• Attended a 3 days social program at SEARCH, Gadchiroli, India.
• Organising member of 5th International Symposium on Semiconductor Materials and Devices (ISSSMD-2018) and 3rd Research Scholar Day at VNIT, Nagpur.

• R. C. Junghare and G. C. Patil, "Performance Comparison of 2D Mono-Elemental (X-enes) Armchair Nanoribbon Schottky Barrier Field Effect Transistors," in IEEE Transactions on Nanotechnology,vol. 23, pp. 408-414, 2024, doi: 10.1109/TNANO.2024.3395986.
• M. K. Vinayak Pachkawade, Rajesh Junghare, Rajendra Patrikar, “Mechanically coupled ring-resonator filter and array (analytical and finite element model),” IET Comput. Digit. Tech., vol. 10, no. 5, pp. 261–267, 2016. Available: 10.1049/iet-cdt.2015.0202.
• R. C. Junghare and G. C. Patil, “Investigation of transport in edge passivated armchair silicene nanoribbon field effect transistor by ab-initio based Wannierised tight binding,” Superlattices Microstruct., vol. 156, p. 106933, 2021, doi: https://doi.org/10.1016/j.spmi.2021.106933.
• Rajesh C. Junghare, Ganesh C. Patil,"Effect of strain on quantum transport in fully-hydrogenated silicene based field effect transistor", Micro and Nanostructures, Volume 172, 2022, 207432, ISSN 2773-0123, https://doi.org/10.1016/j.micrna.2022.207432.
• Junghare, R.C., Patil, G.C. A2D Sim: atom-to-device simulation platform for quantum device simulations. Graphene and 2D mater 9, 263–274 (2024). https://doi.org/10.1007/s41127-024-00084-8

Patent- 1 US patent submitted

• Won Innobvation award for using AI based analysis method for HBM product yield improvement and failure characterization at Micron