RAMA KRISHNA MEDA
Bengaluru
Summary
RTL Design Engineer with 9 years of experience in semiconductor design, including 2 years in ASIC and 7 years in FPGA RTL design. Expertise in Memory Calibration, RTL development, and Hardware Bring-up. Proficient in Xilinx FPGA (16nm–7nm) Vivado flow and IP design, with a strong track record in technical leadership. Recognized for effective cross-functional collaboration and complex debugging skills.
Overview
9
9
years of professional experience
Work History
Staff Design Engineer
Synopsys
06.2023 - Current
- Developed I3C IP features including HDR-BT and HDR-DDR flow control.
- Created new I3C-to-AHB bridge product from inception.
- Contributed to I3C v1.2 specification and reviewed I3C TCRI v1.1.
- Nominated as reviewer and author for I3C HCI new specification.
- Enhanced SpyGlass, VC SpyGlass, and Euclid IDE tools through hands-on improvements.
- Supported cross-functional design, verification, and debugging processes.
- Led team of five members to deliver innovative features for IP products.
Sr Design Engineer, Memory Calibration
Xilinx Inc.
02.2018 - 06.2023
- Developed RTL for DPHY RX Calibration Algorithms on Versal device
- Developed CPHY calibration RTL and partial controller design.
- Executed RLDRAM3 calibration & bring-up; performed RTL/UNISIM simulation for DDR4 PHYs.
- Debugged CDC noise on Ultrascale+ (team award); led QDR4 & DDR4 hardware bring-up.
- Implemented QDR4 calibration RTL , C Algorithms and improved controller performance.
- Implemented DDR4 ASIC calibration RTL for VC400 FPGAs; validated on hardware.
- Migrated 16nm PHY RTL to 7nm; initiated strobe/data centering logic in RTL and C.
- Delivered memory IP firmware packaging for Vivado releases.
RTL & Board Designer
Tejas Networks
08.2016 - 02.2018
- Implemented Application IP on Xilinx FPGA utilizing PCIe Endpoint for Ethernet switch control path.
- Designed Power Management Board for TJ14XX Ethernet switches to enhance efficiency.
- Developed I2C controller RTL in Verilog, ensuring seamless FPGA integration.
- Coordinated firmware and software development for EEPROM, NOR Flash, and PWM fan control.
Education
B.Tech - ECE
National Institute of Technology(NIT Warangal)
GPA: First Class Distinction05-2016
Intermediate(XII) -
Sri Chaitanya Vijayawada
GPA: 97.9 percenatge05-2012
Board of Secondary Education(X) -
Bhashyam
Guntur, GPA: 95 percentage04-2010
Skills
- Protocols: I3C, AHB, APB, QDR4, PCIe, MIPI-C/DPHY, I2C, UART
- Languages: SystemVerilog, Verilog, Python, C, C
- Tools: Verdi, SpyGlass, VC SpyGlass, Vivado, Euclid IDE
- Other: Perforce, Digital Logic, Comp Architecture, System Debug
Accomplishments
- Secured 36th rank in the State-level Common Entrance Test (EAMCET) among 300,000+ candidates.
- Achieved 1335th rank in AIEEE 2012, competing with over 1.3 million candidates nationwide.
- Attained 216th All India Rank in VIT Engineering Entrance Exam 2012.
- Awarded Merit Scholarship at NIT Warangal for academic excellence.
https://www.linkedin.com/in/rama-krishna-meda-43194987
Timeline
Staff Design Engineer
Synopsys
06.2023 - Current
Sr Design Engineer, Memory Calibration
Xilinx Inc.
02.2018 - 06.2023
RTL & Board Designer
Tejas Networks
08.2016 - 02.2018
B.Tech - ECE
National Institute of Technology(NIT Warangal)
Intermediate(XII) -
Sri Chaitanya Vijayawada
Board of Secondary Education(X) -
Bhashyam
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