RASHMI T S

Electrical to Optical Transceiver- IEEE 802.3 dj

• Understanding of PCSL to PMAL muxing in IEEE 802.3 dj/df/ck standards.
• Micro-architecture and System Verilog implementation of Alignment Marker Detection at PMAL which supports IEEE 802.3 dj/df/ck.
• Performed lint checks using Spyglass Lint.
• Perform logical synthesis to find gate count, area and leakage power in Genus.
• Run basic test cases to verify functionality before releasing to verification team.
• Generated verilog register files for RFIC modules using async_rz interface.

Technology Migration for Wifi7

• Understood existing Moortech PVT IP 16nm architecture.
• Developed wrapper around Samsung PVT IP 14nm to be pin compatible with Moortech PVT IP.
• Tools used: Xcelium, Spyglass Lint, Genus.

FPGA Emulation for Ultrawide Band ranging IC

• Bitfile genertion using Vivado.
• Check for hold time violations and fix hold time violation by giving different attributes in Vivado tool and ILA checks.
• Tools used: Vivado, Pycharm, Verdi.

• Implementation of SPI protocol in unidirectional mode.
• Tools Used: Xcelium, Jasper Gold LInt.

• Trained the interns on Verilog, System Verilog, Lint Checks, CDC basics, Synthesis and SDC basics.